Semiconductor booster circuit having cascaded MOS transistors

ABSTRACT

A semiconductor booster circuit includes: a plurality of stages, each having a first MOS transistor and a first capacitor having one terminal connected to a drain terminal of the first MOS transistor, the stages being connected in series by connecting the first MOS transistors of the stages in cascade; and at least one of a first arrangement wherein a source terminal of the first MOS transistor of each of the stages is electrically connected to its substrate, and the substrates of the first MOS transistors in the plurality of stages are electrically insulated from one another, and a second arrangement wherein one terminal of a second capacitor is connected to a gate terminal of the first MOS transistor of each of the stages, and a first clock signal generating unit for inputting a first clock signal to the other terminal of the first capacitor in each stage and a second clock signal generating unit for inputting a second clock signal having a larger amplitude than a power supply voltage (Vdd) to the other terminal of the second capacitor, in each stage are provided.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor booster circuitand more particularly to a semiconductor booster circuit, such as acharge pump circuit, which is used in an EEPROM (Electrically Erasableand Programmabe Read Only Memory) and a flash memory.

[0003] 2. Description of the Related Art

[0004] In recent years, along with the promotion of a single 5V powersupply or the promotion of a single 3V power supply for semiconductorintegrated circuits such as EEPROMs and flash memories, the boosting hasbeen performed in the integrated circuit. As a result, semiconductorbooster circuits such as a Cockcroft Walton circuit and a charge pumpcircuit have been employed.

[0005]FIG. 22 shows a configuration of a conventional semiconductorbooster circuit.

[0006] As shown in the figure, N-channel MOS transistors Q₂₀ to Q₂₄ areconnected in cascade to configure a booster circuit having n stages. Thegate terminals of the transistors Q₂₀ to Q₂₄ are connected to therespective source terminals N₂₀ to N₂₄ to which a clock signal φ_(A) orφ_(B) is input through respective capacitors C₂₀ to C₂₄.

[0007] As shown in FIG. 23, the clock signals φ_(A) and φ_(B) are inopposite phase with each other. Each of the clock signals φ_(A) andφ_(B) has a period of 1/f and an amplitude of V_(φ). The clock signalsφ_(A) and φ_(B) are obtained from a clock signal CK through two NANDcircuits ND₁ and ND₂ and three inverters IV₁ to IV₃, and the amplitudeV_(φ) thereof is equal to a power supply voltage Vdd. Incidentally, inFIG. 22, reference symbol G designates a ground terminal.

[0008] As shown in FIG. 22, in this semiconductor booster circuit, thepower supply voltage Vdd is output as an input signal from a sourceterminal N₂₇ of a transistor Q₂₅, and an output voltage V_(POUT) isoutput as an output signal from an output terminal N₂₆.

[0009] As described in an article “Analysis and Modeling of On-ChipHigh-voltage Generator Circuits for Use in EEPROM Circuits (IEEE JOURNALOF SOLID-STATE CIRCUITS, vol. 24, No. 5, October 1989) for example, theoutput voltage V_(POUT) of a sort of the semiconductor booster circuitis expressed by the following expressions:

V _(POUT) =V _(in) −V _(t) +n([V _(φ) ·[C/(C+C _(s))−V _(t) ]−I _(OUT)/f(C+C _(s))]  (1)

Vt=V _(t0) +K ₂·([Vbs+2_(φf))^(½)−(2_(φf))^(½)]  (2)

[0010] where V_(in) is an input of the booster circuit, V₀ is anamplitude voltage of the clock signal, f is a clock frequency, C is acoupling capacitance to the clock signal, Cs is a parasitic capacitancein each of stages in the booster circuit, n is the number of stages ofthe booster circuit, V_(POUT) is the output voltage in the final stageof the booster circuit, I_(OUT) is a load current in the output stage,Vto is a threshold voltage when a substrate bias is absent, Vbs is asubstrate bias voltage (a potential difference between the source and asubstrate or a well), φ_(f) is a Fermi potential, Vt is a thresholdvoltage of the transistor, and K₂ is a substrate bias coefficient.

[0011] From the expression (1), it is understood that when the loadcurrent I_(OUT) is zero and the relation of C/(C+Cs)=1 is established,the output voltage V_(POUT) is increased in proportion to both a valueof (V_(φ)−Vt) and the number n of stages of the booster circuit. In theconventional booster circuit shown in FIG. 22, since the amplitudevoltage V_(φ) of the clock signal is equal to the power supply voltageVdd, the output voltage V_(POUT) is increased in proportion to both thevalue of (Vdd−Vt) and the number of stages of the booster circuit.

[0012] However, in the conventional booster circuit, there occurs aphenomenon that as the level of the output voltage V_(POUT) isincreased, as shown in the expression (2), the threshold voltage Vt ofeach of the transistors Q₂₀ to Q₂₄ is increased due to the substrateeffect.

[0013] Therefor, in the case where the stages of the booster circuit arediscretely configured in order to prevent the substrate effect fromoccurring, the level of the output voltage V_(POUT) is increased inproportion to the number n of stages of the booster circuit. On theother hand, in the case where the transistors Q₂₀ to Q₂₄ are integratedto be formed on the same substrate, since the substrate effect occurs,as the number n of stages of the booster circuit is increased, the valueof (Vdd−Vt) is decreased.

[0014] As a result, as shown in FIG. 24, along with the increasing ofthe number n of stages of the booster circuit, the output voltageV_(POUT) is decreased to a level lower than a value which is obtainedwhen no substrate effect occurs, and is saturated at the point where thevalue of (Vdd−Vt) becomes zero. This means that no matter how the numbern of stages of the booster circuit is increased, there is a limit in theresultant output voltage V_(POUT). FIG. 25 shows the relationshipbetween the power supply voltage Vdd and a maximum output voltage whenthe number n of stages of the booster circuit is made infinitely large.When the number n of stages of the booster circuit is made infinitelylarge, in the case where no substrate effect occurs, the resultantoutput voltage V_(POUT) becomes theoretically infinite. On the otherhand, in the case where the substrate effect actually occurs, theresultant output voltage V_(POUT) is limited to a value depending on thepower supply voltage Vdd. That is, in the conventional booster circuit;there arises a problem that in the case where the level of the powersupply voltage Vdd is low, the desired output voltage V_(POUT) can notbe obtained even if the number n of stages of the booster circuit is setto any large value.

[0015] For example, in the conventional booster circuit shown in FIG.22, in the case where the power supply voltage Vdd is 2.5V, and thethreshold voltage Vto is 0.6V when no substrate effect occurs (thesubstrate bias voltage is 0V), when the number n of stages of thebooster circuit is set to 20, 20V can be obtained as the output voltageV_(POUT). However, in the case where the power supply voltage Vdd is2.0V, even if the number n of stages of the booster circuit is set to100, only 12V can be obtained as the output voltage V_(POUT).

[0016] On the other hand, in JP-A-61-254078, there is disclosed aCockcroft type booster circuit in which a threshold voltage Vt of a MOStransistor in the subsequent stage having the substrate effect is madelower than that of a MOS transistor in the preceding stage, therebyimproving the reduction of the output voltage due to the substrateeffect.

[0017] However, in this configuration as well, the increase of thethreshold voltage Vt due to the substrate effect can not be suppressed.For example, in the case where the level of the power supply voltage Vddis approximately halved (Vdd=1 to 1.5V), even if the number n of stagesof the booster circuit is set to any value, the desired output voltageV_(POUT) can not be obtained. In addition, since the threshold voltagesVt of the MOS transistors are set to a plurality of different levels,for example, it is necessary to conduct the extra process of photomaskand ion implantation. As a result, the manufacturing process becomescomplicated. This is a disadvantage.

[0018]FIG. 26 shows a configuration of still another conventionalsemiconductor booster circuit.

[0019] As shown in FIG. 26, eight N-channel MOS transistors M₁ to M₈ areconnected in series with one another to configure a booster circuithaving four stages. Gate terminals of the transistors M₁ to M₈ areconnected to respective drain terminals (represented by nodes N₀ to N₇).To the drain terminals N₀, N₂, N₄ and N₆, a clock signal φ_(A) as shownin FIG. 21 is input through capacitors C₁, C₃, C₅ and C₇, respectively.To the drain terminals N₁, N₃, N₅ and N₇, a clock signal φ_(B) which isin opposite phase with the clock signal φ_(A) is input throughcapacitors C₂, C₄, C₆ and C₈, respectively. In addition, substrateterminals of the transistors M₁ to M₈ are connected to a ground terminal(represented by a node N₂₁). In addition, both a drain terminal and agate terminal of each of the N-channel MOS transistors M₂₀ and M₂₁ areconnected to an associated input terminal (represented by a node N₂₀),and a substrate terminal thereof is connected to the ground terminalN₂₁.

[0020] That is, the node N₀ is respectively connected to the sourceterminal of the transistor M₂₀, both the drain terminal and the gateterminal of the transistor M₁, and one terminal of the capacitor C₁. Thenode N₁ is respectively connected to the source terminal of thetransistor M₂₁, both the drain terminal and the gate terminal of thetransistor M₂, the source terminal of the transistor M₁ and one terminalof the capacitor C₂. The node N₂ is respectively connected to both thedrain terminal and the gate terminal of the transistor M₃, the sourceterminal of the transistor M₂ and one terminal of the capacitor C₃. Thenode N₃ is respectively connected to both the drain terminal and thegate terminal of the transistor M₄, the source terminal of thetransistor M₃ and one terminal of the capacitor C₄. The node N₄ isrespectively connected to both the drain terminal and the gate terminalof the transistor M₅, the source terminal of the transistor M₄ and oneterminal of the capacitor C₅. The node N₅ is respectively connected toboth the drain terminal and the gate terminal of the transistor M₆, thesource terminal of the transistor M₅ and one terminal of the capacitorC₆. The node N₆ is respectively connected to both the drain terminal andthe gate terminal of the transistor M₇, the source terminal of thetransistor M₆ and one terminal of the capacitor C₇. In addition, thenode N₇ is respectively connected to both the drain terminal and thegate terminal of the transistor M₈, the source terminal of thetransistor M₇ and one terminal of the capacitor C₈. Further, an outputterminal (represented by a node N₈) of the semiconductor booster circuitis connected to the source terminal of the MOS transistor M₈.

[0021] The above-mentioned expressions (1) and (2) are also applied tothis booster circuit. Then, if the load current I_(OUT) is zero, thecapacitance ratio C/(C+Cs) is 1, and the amplitude voltage V_(φ) of theclock signal is equal to the power supply voltage Vdd in the expression(1), the voltage which is boosted per stage is expressed by (Vdd−Vt).

[0022] Therefore, it is understood that the output voltage V_(POUT) isinfluenced by the margin between the threshold voltage Vt of each of theMOS transistors and the power supply voltage Vdd. In particular, it isunderstood that when the relation of Vt≧Vdd is established, the boostingoperation is not performed in the corresponding stage. That is, if thethreshold voltage Vt is increased, the voltage which is boosted perstage becomes either small or zero. Therefore, even if the number n ofstages of the booster circuit is increased, the output voltage V_(POUT)is hardly or never increased. For example, since the source potential ofthe MOS transistor shown in FIG. 26 is equal to the output voltageV_(POUT), and the substrate potential is 0V, the substrate bias voltageVbs is equal to the output voltage V_(POUT). Now, since the boostercircuit shown in FIG. 26 is provided for generating the positive highvoltage, the output voltage V_(POUT) takes one of positive values.Therefore, the threshold voltage of the MOS transistor M₈ becomes veryhigh, and hence the boosting efficiency is reduced. This problem becomesespecially pronounced during the low power source voltage operation inwhich the margin between the threshold voltage Vt and the power supplyvoltage Vdd is small.

[0023] In this booster circuit, as shown in FIG. 26, all the substrateterminals of the MOS transistors M₁ to M₈ are grounded. That is, the MOStransistors M₁ to M₈ are, as shown in FIG. 27, respectively constitutedby sources/drains 454 to 462, which are formed in a P type semiconductorsubstrate 451, and gates 464 to 471, and the substrate terminal isconnected to a ground terminal N₂₁ through a P⁺ type impurity diffusionlayer 452 in the semiconductor substrate 451. Incidentally, referencenumeral 453 designates a drain of a MOS transistor 20 and referencenumeral 463 designates a gate of the MOS transistor 20.

[0024] Therefore, there arises a problem that the potential of thesource terminal of the MOS transistor, which is located in the morebackward stage, becomes higher, and the difference in the potentialbetween the source terminal and the substrate portion is increased sothat due to the so-called substrate bias effect, the threshold voltageVt is increased, and hence the output voltage V_(POUT) is limited due tothe increase of the threshold voltage Vt.

SUMMARY OF THE INVENTION

[0025] It is therefore an object of the present invention to provide asemiconductor booster circuit in which a desired output voltage iscapable of being obtained, even in the case where a level of a powersupply voltage is low, without the necessity of the complicatedmanufacturing process.

[0026] A semiconductor booster circuit, according to the presentinvention, includes: a plurality of stages, each having a first MOStransistor and a first capacitor having one terminal connected to adrain terminal of the first MOS transistor, the stages being connectedin series by connecting the first MOS transistors of the stages incascade; and at least one of a first arrangement wherein a sourceterminal and a substrate of the first MOS transistor of each of thestages are electrically connected to each other and when the pluralityof stages are divided into at least two groups, the substrates of thefirst MOS transistor included in each group are electrically insulatedfrom the substrates of the first MOS transistors included in a differentgroup and an arrangement wherein one terminal of a second capacitor isconnected to a gate terminal of the first MOS transistor of each of thestages, and first clock signal generating means for inputting a firstclock signal to the other terminal of the first capacitor, and secondclock signal generating means for inputting a second clock signal havinga larger amplitude than a power supply voltage to the other terminal ofthe second capacitor are provided.

[0027] The semiconductor booster circuit, according to a first aspect ofthe present invention, includes a plurality of stages, each having afirst MOS transistor and a first capacitor having one terminal connectedto a drain terminal of the MOS transistor, the stages being connected inseries by connecting the MOS transistors of the stages in cascadewherein a source terminal and a substrate of the first MOS transistor ofeach of the stages are electrically connected to each other and when theplurality of stages are divided into at least two groups, the substratesof the first MOS transistors included in each group are electricallyinsulated from the substrates of the first MOS transistors included in adifferent group.

[0028] In one embodiment of the present invention, the first MOStransistor is a P-channel MOS transistor which is formed in an N typewell region, and the N type well regions of the respective stages areelectrically insulated from one another.

[0029] In one embodiment of the present invention, in each of thestages, a second capacitor having one terminal, which is connected to agate terminal of the first MOS transistor, is provided, and also thegate terminal and the source terminal of the first MOS transistor areconnected to each other through a second MOS transistor, and a gateterminal of the second MOS transistor is connected to the one terminalof the first capacitor.

[0030] In one embodiment of the present invention, a pair of first clocksignals which are in opposite phase with each other are respectivelyinputted to the two other terminals of the first capacitors in the twocontinuous stages, and a pair of second clock signals which aredifferent in pulse timing from each other are respectively inputted tothe two other terminals of the second capacitors in the two continuousstages.

[0031] In one embodiment of the present invention, in each of thestages, the gate terminal of the first MOS transistor in the precedingstage is connected to the one terminal of the first capacitor in thesubsequent stage, and a pair of clock signals which are in oppositephase with each other are respectively inputted to the two otherterminals of the first capacitors in the two continuous stages.

[0032] In one embodiment of the present invention, each of the stagesincludes a first MOS transistor and a first capacitor having oneterminal connected to a source terminal of the first MOS transistor,wherein the stages are connected in series by connecting the first MOStransistors of the respective stages in cascade, a gate terminal and thesource terminal of the first MOS transistor in each stage areelectrically connected to each other, and also the source terminal andthe substrate thereof are electrically connected to each other and thesubstrate is electrically insulated from the substrate of the first MOStransistors in another stage.

[0033] Incidentally, in a preferred aspect of the present invention, thefirst MOS transistor is an N-channel MOS transistor which is formed in aP type well region, and the P type well regions of the respective stagesare electrically insulated from one another.

[0034] In the first aspect of the present invention, the substrate ofthe MOS transistor forming each of the stages of the booster circuit iselectrically insulated from the substrate of the MOS transistor ofanother stage, and in each of the stages, the substrate and the sourceterminal of the MOS transistor are electrically connected to each other,whereby the potential at the substrate of the MOS transistor is fixed tothe source potential. Hence the increase of the threshold voltage of theMOS transistor due to the substrate effect is effectively suppressed.

[0035] A semiconductor booster circuit, according to a second aspect ofthe present invention, includes: a plurality of stages, each having afirst MOS transistor, a first capacitor having one terminal connected toa drain terminal of the first MOS transistor, and a second capacitorhaving one terminal connected to a gate terminal of the first MOStransistor, the stages being connected in series by connecting the firstMOS transistors in the respective stages in cascade; first clock signalgenerating means for inputting a first clock signal to the otherterminal of the first capacitor and second clock signal generating meansfor inputting a second clock signal having a larger amplitude than apower supply voltage to the other terminal of the second capacitor.

[0036] In one embodiment of the present invention, the first clocksignal includes a pair or clock signals which are in opposite phase witheach other, and the pair of clock signals are respectively inputted tothe two first capacitors in the two consecutive stages.

[0037] In one embodiment of the present invention, in each of thestages, the gate terminal and the drain terminal of the first MOStransistor are connected to each other through a second MOS transistor,and a gate terminal of the second MOS transistor is connected to theother terminal of the first capacitor in the subsequent stage.

[0038] In the second aspect of the present invention, in order to drivethe MOS transistors to perform the boosting operation, other clocksignals are employed which are different from the clock signals whichare used to drive the stages and have a larger amplitude than the powersupply voltage, whereby it is possible to secure the threshold forconducting the MOS transistor and also it is possible to prevent thereduction of the output voltage due to the substrate effect.

[0039] A semiconductor booster circuit, according to a third aspect ofthe present invention, includes: a plurality of stages, each having afirst MOS transistor and a first capacitor having one terminal connectedto a drain terminal of the first MOS transistor, the stages beingconnected in series by connecting the first MOS transistors of therespective stages in cascade, wherein a source terminal and a substrateof the first MOS transistor in each of the stages are electricallyconnected to each other, and when the plurality of stages are dividedinto at least two stages, the substrates of the first MOS transistorsincluded in each group are electrically insulated from the substrates ofthe first MOS transistors included in another group; and wherein oneterminal of a second capacitor is connected to a gate terminal of thefirst MOS transistor in each of the stages, and first clock signalgenerating means for inputting a first clock signal to the otherterminal of the first capacitor in each stage, and second clock signalgenerating means for inputting a second clock signal having a largeramplitude than a power supply voltage to the other terminal of thesecond capacitor in each stage are provided.

[0040] In one embodiment of the present invention, the first MOStransistor is a P-channel MOS transistor which is formed in an N typewell region, and the N type well regions in the respective stages areelectrically insulated from one another.

[0041] In one embodiment of the present invention, in each of thestages, the gate terminal and the source terminal of the first MOStransistor are electrically connected to each other through a second MOStransistor, and a gate terminal of the second MOS transistor isconnected to the one terminal of the first capacitor.

[0042] In one embodiment of the present invention, the first clocksignal includes a pair of clock signals which are in opposite phase witheach other, and the pair of clock signals are respectively inputted tothe first capacitors in the two consecutive stages.

[0043] In the third aspect of the present invention, the substrate ofthe MOS transistor constituting each of the stages of the boostercircuit is electrically insulated from the substrate of the MOStransistor in another stage, and also in each of the stages, thesubstrate and the source terminal of the MOS transistor are electricallyconnected to each other, whereby the potential at the substrate of theMOS transistor is fixed to the source potential. Hence the increase ofthe threshold voltage of the MOS transistor due to the substrate effectis suppressed.

[0044] In addition, the gate voltage of the MOS transistor whichoperates to perform the boosting operation in the stages is controlledby the clock signals other an the source voltage and the drain voltage,and the amplitude of each of the clock signals is made larger than theinput power supply voltage of the booster circuit, whereby since even inthe employment of the low power supply voltage, the MOS transistor canbe sufficiently rendered to an on state, and also the voltage drop dueto the threshold voltage of the MOS transistor is eliminated so that theboosting capability is improved.

[0045] A semiconductor booster circuit, according to a fourth aspect ofthe present invention, includes a plurality of stages, each of thestages having two first MOS transistors which are connected in serieswith each other and two capacitors, each having one terminal connectedto a drain or source terminal of one of the first MOS transistors, theseries circuits of the first MOS transistors of the respective stagesbeing connected in series between an input side and an output side,wherein the plurality of stages are divided into at least two groups,and substrates of the first MOS transistors included in the stages ofeach group are formed integrally in a conductive substrate portion, andthe potentials which are applied to the substrate portions of the groupsare controlled independently of one another.

[0046] In one embodiment of the present invention, the booster circuitoperates for generating a positive high voltage and the substrateportions of the first MOS transistors included in the more backwardstage are controlled at a higher potential.

[0047] In one embodiment of the present invention, the first MOStransistor is a P-channel MOS transistor which is formed in an N typewell region, and the N type well regions of the respective groups areelectrically insulated from one another.

[0048] In one embodiment of the present invention, the booster circuitoperates for generating a negative high voltage and the substrateportions of the first MOS transistors included in the more backwardstage are controlled at a negative lower potential.

[0049] In one embodiment of the present invention, the first MOStransistor is an N-channel MOS transistor which is formed in a P typewell region, and the P type well regions of the respective groups areelectrically insulated from one another.

[0050] In one embodiment of the present invention, the substrate of thefirst MOS transistor of each stage is connected to a drain terminal or asource terminal of the first MOS transistor which is located at thepreceding stage of the group to which the first MOS transistor belongs.

[0051] In one embodiment of the present invention, second capacitorseach having one terminal connected to the gate terminal of one of thefirst MOS transistors are provided, and the gate terminal and the sourceor drain terminal of each of the first MOS transistors are connected toeach other through a second MOS transistor, and the gate terminal of thesecond MOS transistor is connected to the one terminal of the firstcapacitor.

[0052] In one embodiment of the present invention, in each of thestages, the substrate of the second MOS transistor is connected to thesubstrate of the first MOS transistor.

[0053] In one embodiment of the present invention, a pair of first clocksignals which are in opposite phase with each other are respectivelyinputted to the other terminals of the two adjacent first capacitors,and also a pair of second clock signals which are different in pulsetiming from each other are respectively inputted to the other terminalsof the two adjacent second capacitors.

[0054] In the fourth aspect of the present invention, since thesubstrate portions of the MOS transistors constituting the boostercircuit are divided into groups and the potentials of the substrateportions in the respective groups are controlled independently of oneanother, the potentials at the substrate portions of the MOS transistorsof each group can be fixed to a potential different from that of anothergroup. Therefore, it is possible to suppress the increase of thethreshold voltage of the MOS transistor due to the substrate biaseffect, and also the level of the output voltage can be made higher thanthat in the conventional booster circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0055]FIG. 1 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a first embodiment of thepresent invention;

[0056]FIG. 2 is a circuit diagram showing a configuration of the twocontinuous stages of the semiconductor booster circuit according to thefirst embodiment shown in FIG. 1;

[0057]FIG. 3 is a timing chart showing the timing of clock pulses usedin the semiconductor booster circuit shown in FIG. 1;

[0058]FIGS. 4A to 4D are respectively graphical representations showingwaveforms of voltages at respective nodes of the semiconductor boostercircuit shown in FIG. 1;

[0059]FIGS. 5A to 5F are respectively circuit diagrams useful inexplaining the operation of the semiconductor booster circuit shown inFIG. 1;

[0060]FIG. 6 is a cross sectional view showing a device structure of thesemiconductor booster circuit shown in FIG. 1;

[0061]FIG. 7 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a second embodiment of thepresent invention;

[0062]FIG. 8 is a timing chart showing clock pulses used in thesemiconductor booster circuit shown in FIG. 6;

[0063]FIG. 9 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a third embodiment of thepresent invention;

[0064]FIG. 10 is a cross sectional view showing a device structure ofthe semiconductor booster circuit shown in FIG. 9;

[0065]FIG. 11 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a fifth embodiment of thepresent invention;

[0066]FIG. 12 is a timing chart showing clock pulse used in thesemiconductor booster circuit shown in FIG. 11;

[0067]FIG. 13 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a sixth embodiment of thepresent invention;

[0068]FIG. 14 is a cross sectional view showing a device structure ofthe semiconductor booster circuit shown in FIG. 13;

[0069]FIG. 15 is a circuit diagram showing a configuration of asemiconductor booster circuit according to a seventh embodiment of thepresent invention;

[0070]FIG. 16 is a timing chart showing clock pulses used in thesemiconductor booster circuit shown in FIG. 13;

[0071]FIG. 17 is a timing chart showing clock pulses used in thesemiconductor booster circuit shown in FIG. 15;

[0072]FIG. 18 is a circuit diagram showing a configuration of aconventional semiconductor booster circuit;

[0073]FIG. 19 is a timing chart showing clock pulses used in theconventional prior art semiconductor booster circuit;

[0074]FIG. 20 is a graphical representation showing the relationshipbetween the number of stages and an output voltage of the conventionalprior art semiconductor booster circuit;

[0075]FIG. 21 is a graphical representation showing the relationshipbetween a power supply voltage and a maximum output voltage when thenumber of stages of the conventional prior art semiconductor boostercircuit is infinite;

[0076]FIG. 22 is a circuit diagram showing a configuration of anotherconventional prior art semiconductor booster circuit; and

[0077]FIG. 23 is a cross sectional view showing a device structure ofanother conventional prior art semiconductor booster circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0078] A first embodiment of the present invention will hereinafter bedescribed in detail with reference to FIGS. 1 to 10.

[0079]FIG. 1 shows a configuration of a semiconductor booster circuitaccording to the first embodiment of the present invention.

[0080] As shown in FIG. 1, n elements of P-channel MOS transistors Q₁,Q₃, Q₅, Q₇, . . . , Q₉ are connected in cascade to configure a boostercircuit having n stages. Substrate portions of the transistors Q₁, Q₃,Q₅, Q₇, . . . , Q₉ are electrically insulated from one another and alsoare connected to source terminals of the transistors Q₁, Q₃, Q₅, Q₇, . .. , Q₉, respectively. In addition, to drain terminals (represented bynodes N₁, N₃, N₅, N₇, . . . , N₉) a clock signal φ_(1A) or φ_(1B) whichis shown in FIG. 3 is inputted through respective capacitors C₁, C₃, C₅,C₇, . . . , C₉.

[0081] In addition, to gate terminals (represented by nodes N₂, N₄, N₆,N₈, . . . , N₁₀) of the transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉, a clocksignal φ_(2A) or φ_(2B) which is shown in FIG. 3 is inputted throughrespective capacitors C₂, C₄, C₆, C₈, . . . , C₁₀.

[0082] Further, P-channel MOS transistors Q₂, Q₄, Q₅, Q₈, . . . , Q₁₀are respectively connected between the gate terminals N₂, N₄, N₆, N₈, .. . , N₁₀ and source terminals (represented by nodes N₃, N₅, N₇, N₁₁, .. . , N₁₂) of the transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉, and gateterminals of the transistors Q₂, Q₄, Q₆, Q₈, . . . , Q₁₀ arerespectively connected to the drain terminals N₁, N₃, N₅, N₇, . . . , N₉of the transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉.

[0083] In the booster circuit of the present embodiment, a power supplyvoltage Vdd is inputted as an input signal from a common source terminal(represented by a node N₀) of N-channel MOS transistors Q₁₂ and Q₁₃ tothe source terminals N₁ and N₃ of the transistors Q₁ and Q₃, and anoutput voltage V_(POUT) is outputted as an output signal from an outputterminal (represented by a node N₁₃) through an N-channel MOS transistorQ₁₁. As shown in the figure, the gate terminals of the transistors Q₁₂and Q₁₃ are respectively connected to the source terminal N₀. Inaddition, to a source terminal (represented by a node N₁₂) of thetransistor Q₁₁, the clock signal φ_(1A) which is shown in FIG. 3 isinputted through a capacitor C₁₁. Further, a gate terminal of thetransistor Q₁₁ is connected to a drain terminal (represented by the nodeN₁₃).

[0084] As shown in FIG. 3, the clock signals φ_(1A) and φ_(1B) are inopposite phase with each other and have the same amplitude as the powersupply voltage Vdd, and the clock signals φ_(2A) and φ_(2B) arepulse-like signals which have the amplitude equal to or larger than thepower supply voltage Vdd and are in an off-state at periods when theclock signals φ_(1A) and φ_(1B) are in an on-state, respectively.

[0085] As for a clock signal generating unit 120 which operates togenerate the clock signals φ_(1A) and φ_(1B), the same as theconventional unit may be employed. As for clock signal generating units140 and 160 which operate to generate the clock signals φ_(2A) andφ_(2B), respectively, any units may be employed which operate to receiveclock pulse signals CLK₂ and CLK₃ of the same timings as those of thegenerating timings of the clock signals φ_(2A) and φ_(2B), respectively,and control the amplitudes thereof.

[0086] Next, the description will hereinbelow be given with respect tothe operation of the semiconductor booster circuit according to thefirst embodiment with reference to FIGS. 2 to 5.

[0087]FIG. 2 is a circuit diagram showing a configuration of twoconsecutive stages (a first stage and a second stage) of thesemiconductor booster circuit shown in FIG. 1. In addition, FIGS. 4A to4D show waveforms of the voltages at nodes N_(A) to N_(D) of the circuitof FIG. 2 for a time period ranging from (I) to (VI) shown in FIG. 3.Further, FIGS. 5A to 5F are respectively circuit diagrams useful inexplaining the conduction state of transistors M₁ to M₄ of FIG. 2 for atime period ranging from (I) to (VI).

[0088] Firstly, for a period of time of (I), as shown in FIG. 3, thelevel of the clock signal φ_(1A) is raised from the ground potential upto the power supply voltage Vdd, and also the potential at the drainterminal N_(A) of the transistor M₁ shown in FIG. 2 is, as shown in FIG.4A, raised by a voltage corresponding to the power supply voltage Vdd.

[0089] At the same time, the level of the clock signal φ_(1B) is droppedfrom the power supply voltage Vdd down to the ground potential 0V, analso the potential at the source terminal N_(B) of the transistor M₁ is,as shown in FIG. 4B, dropped by a voltage corresponding to the powersupply voltage Vdd.

[0090] At this time, the electric charges which have been transferredfrom the preceding stage are accumulated in the capacitor C_(A2) whichis connected to the source terminal N_(B) of the transistor M₁, andhence the potential at the source terminal N_(B) of the transistor M₁ israised by a voltage corresponding to the electric charges accumulated inthat capacitor C_(A2).

[0091] In addition, the potential at the gate terminal N_(A) of thetransistor M₂ becomes higher than that at the source terminal N_(B), andhence the transistor M₂ is, as shown in FIG. 5A, switched from the onstate to the off state.

[0092] At this time, as will be described later, since the P_(N)junction which is formed between the drain terminal N_(A) and the sourceterminal N_(B) of the transistor M₁ is biased in the forward direction,the substrate portion of the transistor M₁ which is connected to thesource terminal N_(B) is maintained at the potential which is obtainedby subtracting the forward bias voltage across the P_(N) junction fromthe potential at the drain terminal N_(A).

[0093] In addition, as shown in FIG. 4C, the potential at the gateterminal N_(C) of the transistor M₁ is dropped down to the samepotential as that at the drain terminal N_(A), but the transistor M₁remains, as shown in FIG. 5A, in the off state.

[0094] As the level of the clock signal φ_(1A) is raised from the groundpotential 0V up to the power supply voltage Vdd, the potential at thesource terminal N_(D) of the transistor M₃ is, as shown in FIG. 4D,raised by a voltage corresponding to the power supply voltage Vdd.

[0095] At this time, the electric charges which have been transferredfrom the preceding stage are accumulated in the capacitor C_(A3), andhence the potential at the source terminal N_(D) of the transistor M₃ israised by a voltage corresponding to the electric charges accumulated inthe capacitor C_(A3).

[0096] In addition, at the time when the level of the clock signalφ_(1B) has been dropped from the power supply voltage Vdd down to theground potential 0V, the potential at the gate terminal N_(B) of thetransistor M₄ is dropped and hence the transistor M₄ is switched fromthe off state to the on state. Therefore, the potential at the gateterminal N_(E) of the transistor M₃ becomes the same potential as thatat the source terminal N_(D) of the transistor M₃. At this time, asshown in FIG. 5A, the transistor M₃ remains in the off state.

[0097] Next, for a period of time (II), the level of the clock signalφ_(2A) is dropped from the power supply voltage Vdd down to the groundpotential 0V, and hence the potential at the gate terminal N_(C) of thetransistor M₁ is, as shown in FIG. 4C, dropped by a voltagecorresponding to the power supply voltage Vdd.

[0098] As a result, as shown in FIG. 5B, the transistor M₁ is turned onand hence a current is caused to flow from the drain terminal N_(A) tothe source terminal N_(B) of the transistor M₁ until the potential atthe drain terminal N_(A) becomes equal to that at the source terminalN_(B).

[0099] That is, the electric charges are transferred from the capacitorC_(A1) to the capacitor C_(A2), and hence the potential at the drainterminal N_(A) of the transistor M₁ is, as shown in FIG. 4A, dropped,and also the potential at the source terminal N_(B) of the transistor M₁is, as shown in FIG. 4B, raised.

[0100] In addition, with respect to the source terminal N_(D) of thetransistor M₃ as well, in the same manner as that in the case of thedrain terminal N_(A) of the transistor M₁, as shown in FIG. 4D, thepotential at the source terminal N_(D) is dropped.

[0101] At this time, the clock signal φ_(2A) which is used to turn thetransistor M₁ on is supplied from the outside through the capacitorC_(B1), and no voltage drop occurs between the drain terminal N_(A) andthe source terminal N_(B) when turning the transistor M₁ on. Therefore,as compared with the prior art, the boosting capability is furtherimproved. That is, in the above-mentioned expression (1), this statecorresponds to the situation in which in the term within the brackets,Vt is equal to 0V. Thus, the boosting operation can be performed with anexceptionally good efficiency.

[0102] Next, for a period of time (III), the level of the clock signalφ_(2A) is raised from the ground potential 0V up to the power supplyvoltage Vdd, and hence the potential at the gate terminal N_(C) of thetransistor M₁ is, as shown in FIG. 4C, raised by a voltage correspondingto the power supply voltage Vdd.

[0103] As a result, as shown in FIG. 5C, the transistor M₁ is turnedoff.

[0104] In addition, as shown in FIG. 4A, 4B and 4D, the potential at thedrain terminal N_(A) and the source transistor N_(B) of the transistorM₁, and the potential at the source terminal N_(D) of the transistor M₃do not change.

[0105] Next, for a period of time (IV), the level of the clock signalφ_(1A) is dropped from the power supply voltage Vdd down to the groundpotential 0V, and hence the potential at the drain terminal N_(A) of thetransistor M₁ is forced to drop by a voltage corresponding to the powersupply voltage Vdd. However, in the first stage, since the transistorQ₁₂ shown in FIG. 1 goes to the on state, as shown in FIG. 4A, thepotential at the drain terminal N_(A) of the transistor M₁ goes to thepotential of (Vdd−Vt).

[0106] In addition, the level of the clock signal φ_(1B) is raised fromthe ground potential 0V up to the power supply voltage Vdd, and hencethe potential at the source terminal N_(B) of the transistor M₁ is, asshown in FIG. 4B, raised by a voltage corresponding to the power supplyvoltage Vdd.

[0107] At this time, since the electric charges which have beentransferred from the preceding stage are accumulated in the capacitorC_(A2), the potential at the source terminal N_(B) of the transistor M₁is raised by a voltage corresponding to the electric charges accumulatedin the capacitor C_(A2).

[0108] In addition, the potential at the gate terminal N_(A) of thetransistor M₂ becomes lower than that at the source terminal N_(B)thereof, and hence the transistor M₂ is, as shown in FIG. 5D, switchedfrom the off state to the on state.

[0109] As a result, the potential at the gate terminal N_(C) of thetransistor M₁ is, as shown in FIG. 4C, raised up to the same potentialas that at the source terminal N_(B) of the transistor M₁.

[0110] In addition, as the level of the clock signal φ_(1A) is droppedfrom the power supply voltage down to the ground potential 0V, thepotential at the source terminal N_(D) of the transistor M₃ is, as shownin FIG. 4D, dropped by a voltage corresponding to the power supplyvoltage Vdd.

[0111] At this time, the electric charges which have been transferredfrom the preceding stage are accumulated in the capacitor C_(A3), andhence the potential at the source terminal N_(D) is raised by a voltagecorresponding to the electric charges accumulated in the capacitorC_(A3).

[0112] As a result, the potential at the drain terminal N_(E) of thetransistor M₄ becomes higher than that at the source terminal N_(D)thereof, and hence the transistor M₄ is, as shown in FIG. 5D, switchedfrom the on state to the off state.

[0113] In addition, in the same manner as that in the case of theabove-mentioned transistor M₁, since the PN junction which is formedbetween the drain terminal N_(B) and the source terminal N_(D) of thetransistor M₃ is biased in the forward direction, the substrate portionof the transistor M₃ connected to the source terminal N_(D) ismaintained at a voltage which is obtained by subtracting the forwardbias voltage across the PN junction from the potential at the drainterminal N_(B).

[0114] Next, for a period of time of (V), the level of the clock signalφ_(2B) is dropped from the power supply voltage Vdd down to the grouppotential 0V, and hence the potential at the gate terminal N_(E) of thetransistor M₃ is dropped by a voltage corresponding to the power supplyvoltage Vdd.

[0115] As a result, as shown in FIG. 5E, the transistor M₃ is turned on,and also a current is caused to flow from the drain terminal N_(B) tothe source terminal N_(D) of the transistor M₃ until the potential atthe drain terminal N_(B) becomes equal to that at the source terminalN_(D).

[0116] That is, the electric charges are transferred from the capacitorC_(A2) to the capacitor C_(A3), and hence as shown in FIG. 4B, thepotential at the drain terminal N_(B) of the transistor M₃ is droppedand also as shown in FIG. 4D, the potential at the source terminal N_(D)of the transistor M₃ is raised.

[0117] In addition, since the transistor M₂ remains in the on state, andthe potential at the gate terminal N_(C) of the transistor M₁ is equalto that at the drain terminal N_(B) of the transistor M₃, as shown inFIG. 4C, the potential at the gate terminal NC of the transistor M₁ isdropped.

[0118] At this time, the clock signal φ_(2B) which is used to turn thetransistor M₃ on is supplied from the outside through the capacitor C₃₂,and no voltage drop occurs between the drain terminal N_(B) and thesource terminal, N_(D) when turning the transistor M₃ on. Therefore, ascompared with the prior art, the boosting capability is furtherimproved.

[0119] Next, for a period of time of (VI), the level of the clock signalφ_(2B) is raised from the ground potential 0V up to the power supplyvoltage Vdd, and hence the potential at the gate terminal N_(E) of thetransistor M₃ is raised by a voltage corresponding to the power supplyvoltage Vdd.

[0120] As a result, as shown in FIG. 5F, the transistor M₃ goes to theoff state.

[0121] In addition, as shown in FIGS. 4A to 4D, the potentials at thenodes N_(A) to N_(D) do not change.

[0122] In the operation of prior art as described above, since thesource terminals of the transistors M₁ to M₃ are boosted such that thesource terminal of the transistor located in the subsequent stagebecomes higher, the substrate effect acts inherently to raise, as shownin the above-mentioned expression (2), the threshold voltage Vt of eachof the transistors M₁ and M₃. However, in the present embodiment, asshown in FIG. 2, since the substrate portions of the transistors M₁ andM₃ are connected to the source terminal, no substrate effect occurs, andhence the transfer of the electric charges from the preceding stage tothe subsequent stage is effectively performed.

[0123]FIG. 6 is a schematic cross sectional view showing a devicestructure of the transistors M₁ and M₃ shown in FIG. 2.

[0124] As shown in FIG. 6, two N type well regions 11 are respectivelyformed in a P type semiconductor substrate 10 so as to be insulated fromeach other, and in each of the N type well regions 11, there is formed aMOS transistor which includes a polycrystalline silicon layer 16, as agate electrode, which is formed on the substrate portion of the well 11with a gate oxide film 15 disposed therebetween, and P⁺ type impuritydiffusion layers 12 as source/drain regions.

[0125] The P⁺ type impurity diffusion layer 12 of the source side ineach of the transistors is electrically connected to the N type wellregion 11, in which the transistor is formed, through a N⁺ type impuritydiffusion layer 14, and the source of the transistor in the precedingstage is connected to the drain of the transistor in the subsequentstage.

[0126] By adopting this structure, the potential at the N type wellregion 11 as the substrate portion of each of the transistors is fixedto the source potential of each of the transistors, and hence thesubstrate effect can be effectively prevented from occurring.

[0127] In addition, for a period of time of (I) of FIG. 5A or (IV) ofFIG. 5D, the PN junction which is formed between the P⁺ type impuritydiffusion layer 12 of the drain side and the N type well region 11 ofeach of the transistors is biased in the forward direction. Then,through that PN junction, the electric charges can be transferred fromthe node N_(A) to the node N_(B) and from the node N_(B) to the nodeN_(D) through the N type well region 11 of the substrate and the N⁺ typeimpurity diffusion layer 14. In this case, the voltage differencecorresponding to the forward bias voltage V_(F) (normally, about 0.7V)across the PN junction which is independent of the threshold voltage Vtof the MOS transistor is utilized for the boosting operation, and henceV_(F) is employed instead of Vt in the above-mentioned expressions (1)and (2). Since the forward bias voltage V_(F) across the PN junction isnot influenced by the substrate effect, it is possible to realize thebooster circuit which, even when the number of stages of the boostercircuit is increased, is free from the reduction of the boostingcapability due to the substrate effect.

[0128] As described above, in the semiconductor booster circuitaccording to the first embodiment of the present invention, thesubstrate portions of the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉shown in FIG. 1 are electrically insulated from one another, and alsothe substrate portions are respectively connected to the sourceterminals N₃, N₅, N₇, N₁₁, . . . , N₁₂, whereby the increase of thethreshold voltage Vt due to the substrate effect is effectivelyprevented. Therefore, it is possible to obtain the output voltageV_(POUT) which is increased in proportion to the number n of stage ofthe booster circuit and also it is possible to provide the semiconductorbooster circuit which has the higher boosting capability than that ofthe prior art.

[0129] In addition, with respect to the structure of the presentembodiment, as shown in FIG. 6, the N type well regions 11 in which therespective transistors are formed are isolated from each other and alsothe N⁺ type impurity region 14 of each of the N type well regions 11 iselectrically connected to the P⁺ type impurity region 12 of the sourceside of each of the transistors. Thus, the process for making thethreshold voltages of the respective transistors different from oneanother, as in the prior art, is not required at all. Therefore, thenumber of manufacturing processes is not increased much.

[0130] In addition, the substrate portion of each transistor iselectrically connected to the source terminal, whereby the PN junctionwhich is formed in the boundary between the drain and the substrateportion is connected in parallel between the source and drain of thetransistor. Then, when transferring the electric charges from thepreceding stage to the subsequent stage in the booster circuit, the PNjunction is biased to the on state, whereby the potential at thesubstrate portion of each transistor can be fixed to a voltagedifference corresponding to the forward bias voltage V_(F) (normally,about 0.7V) across the PN junction. Thus, it is possible to suppress theinfluence of the substrate effect.

[0131] In addition, as shown in FIG. 5, to the gate terminals N_(C) andN_(E) of the transistors M₁ and M₃, the pair of clock signals φ_(2A) andφ_(2B) which are independent from the pair of clock signals φ_(1A) andφ_(1B) respectively inputted to the drain terminals N_(A) and N_(B), arerespectively inputted, whereby each of the transistors M₁ and M₃ can beturned on in such a way that no potential difference occurs between thesource and the drain thereof. Therefore, when transferring the electriccharges from the preceding stage to the subsequent stage in the boostercircuit, it is possible to realize the transfer of the electric chargessuch that the voltage drop does not occur which corresponds to thepotential difference between the source and the drain. Therefore, sincein the above-mentioned expression (1), the threshold voltage Vt can beregarded as zero, the boosting operation can be more efficientlyperformed as compared with the conventional booster circuit. Even thecase where the number n of stages of the booster circuit and the powersupply voltage Vdd are the same as those of the conventional boostercircuit, the larger output voltage V_(POUT) can be obtained. Inaddition, in the case where the output voltage V_(POUT) is the same asthat of the conventional booster circuit, the booster circuit of thepresent embodiment can obtain the larger load current I_(OUT).

[0132] For example, in the case where the power supply voltage Vdd is20V, and the number n of stages of the booster circuit is 20, assumingthat the capacitance ratio C/(C+Cs) is 0.9, the absolute value of thethreshold voltage |Vt| is 0.6, and the load current I_(OUT) of theoutput stage is zero, only 20V can be obtained as the output voltageV_(POUT) in the conventional booster circuit, but in the booster circuitaccording to the present embodiment, about 47V can be obtained.

[0133] In addition, in the semiconductor booster circuit according tothe present embodiment, even in the low power supply voltage Vdd whichcan not be boosted by the conventional booster circuit, the desiredoutput can be obtained. In other words, in the conventional boostercircuit, as shown in FIG. 25, even if the number n of stages of thebooster circuit is set to any value, the maximum output voltage islimited to a predetermined value depending on the power supply voltageVdd. However, in the semiconductor booster circuit according to thepresent embodiment, such a limit is not present substantially.

[0134] For example, in the case where the power supply voltage Vdd is2.0V, assuming that the capacitance ration C/(C+Cs) is 0.9, the absolutevalue of the threshold voltage |Vt| is 0.6V, and the load currentI_(OUT) in the output stage is zero, even in the booster circuit inwhich the number n of stages of the booster circuit is 50, only 12V canbe obtained as the output voltage V_(POUT) in the conventional boostercircuit. In the booster circuit according to the present embodiment,when the number n of stages of the booster circuit is 20, about 37V canbe obtained as the output voltage V_(POUT), and also when the number nof stages of the booster circuit is 50, about 91V can be obtained.

[0135] Incidentally, in the semiconductor booster circuit according tothe present embodiment, in the case where the absolute value of thethreshold voltage |Vt| is set to 0.6V, the lower limit of the boostablepower supply voltage Vdd is about 0.7V.

[0136] In the above explanation, the substrates of the MOS transistorsin n stages are electrically insulated from each other. Alternatively,the n stages are divided into at least two groups, for example twogroups i.e. a first group of the first to third stages and a secondgroup of the fourth to sixth stages. The substrates of the MOStransistors included in each group are electrically insulated form thesubstrates of the MOS transistors included in the other group.

[0137] Next, the description will hereinbelow be given with respect to asemiconductor booster circuit according to a second embodiment of thepresent invention with reference to FIGS. 7 and 8.

[0138]FIG. 7 is a circuit diagram showing a configuration of thesemiconductor booster circuit according to the second embodiment of thepresent invention.

[0139] In FIG. 7, n elements of P-channel MOS transistors Q₃₀ to Q₃₄ areconnected in cascade to configure a booster circuit having n stages.Substrate portions of the respective transistors Q₃₀ to Q₃₄ areelectrically insulated from one another, and also gate terminals and thesubstrate portions are connected to respective source terminals N₁ toN₃₅. Then, a clock signal φ_(A) or φ_(B) which is shown in FIG. 8 isinputted to the source terminals N₃₀ to N₃₅ through capacitors C₃₀ toC₃₅, respectively.

[0140] In the booster circuit of the present embodiment, as an inputtedsignal, the power supply voltage Vdd is inputted from a source terminalN₃₇ of a P-channel MOS transistor Q₃₆ to a drain terminal N₃₀ of thetransistor Q₃₀. As an output signal, an output voltage V_(POUT) isoutputted from an output terminal N₃₆ through a P-channel MOS transistorQ₃₅.

[0141] The clock signals φ_(A) and φ_(B) are, as shown in FIG. 8, inopposite phase with each other and have the amplitude of a voltageV_(φ).

[0142] In addition, the device structure of the transistors Q₃₀ to Q₃₄of the present embodiment may be the same as that shown in FIG. 6. Thatis, the N type well regions 11 are formed in the P type semiconductorsubstrate, and in each of the N type well regions 11, thepolycrystalline silicon layer 16 which is formed on the substrateportion of the well region 11 with an intermediate gate oxide film 15therebetween is provided as the gate electrode, and also the P⁺ typeimpurity diffusion layer 12 is provided as the source/drain region. Insuch a manner, the MOS transistor is formed.

[0143] The P⁺ type impurity diffusion layer 12 of the source side ofeach of the transistors is connected to the N type well region 11through the N⁺ type impurity diffusion layer 14, and also the source ofthe transistor in the preceding stage is connected to the drain of thetransistor in the subsequent stage. As a result, the potential at the Ntype well region as the substrate portion of each of the transistors isfixed to the source potential of each of the transistors, and hence thesubstrate effect is effectively prevented from occurring.

[0144] In addition, the PN junction, which is formed between the P⁺ typeimpurity diffusion layer 12 of the drain side and the N type well regionof each of the transistors, is biased in the forward direction, wherebythrough that PN junction, the electric charges are transferred from thenode N_(A) to the node N_(B) and from the node N_(B) to the node N_(D)through the N type well region 11 of the substrate portion and the N⁺type impurity diffusion layer 14. In the case of the present embodiment,each transistor is not rendered substantially perfectly conductiveunlike the state as shown in FIGS. 5B and 5E of the above-mentionedfirst embodiment, and hence the transfer of the electric charges fromthe preceding stage to the subsequent stage is performed through theabove-mentioned PN junction. Therefore, in the case of the presentembodiment, the potential difference corresponding to the forward biasvoltage V_(F) (normally, about 0.7V) across the PN junction which isindependent of the threshold voltage Vt of the MOS transistor isutilized for the boosting operation, and also V_(F) is employed insteadof Vt in the above-mentioned expressions (1) and (2). Since the forwardbias voltage V_(F) across the PN junction is not influenced by thesubstrate effect at all, it is possible to realize the booster circuitin which even when the number of stages of the booster circuit isincreased, the reduction of the boosting capability due to the substrateeffect does not occur at all.

[0145] More specifically, in the present embodiment, as shown in FIG. 7,the substrate portions of the transistors Q₃₀ to Q₃₄ are electricallyconnected to the source terminals N₃₁ to N₃₅, respectively, whereby thePN junction which is formed in the boundary between the drain and thesubstrate portion is connected in parallel between the source and thedrain of each of the transistors Q₃₀ to Q₃₄. Then, when transferring theelectric charges from the preceding stage to the subsequent stage in thebooster circuit, the PN junction is rendered conductive, whereby thepotential at the substrate portion of each of the transistors Q₃₀ to Q₃₄can be fixed to the potential difference corresponding to the forwardbias voltage V_(F) (normally, about 0.7V) across the PN junction.Therefore, it is possible to suppress the influence of the substrateeffect.

[0146] Next, the description will hereinbelow be given with respect to asemiconductor booster circuit according to a third embodiment of thepresent invention with reference to FIGS. 9 and 10.

[0147]FIG. 9 is a circuit diagram showing a configuration of thesemiconductor booster circuit according to the third embodiment of thepresent invention.

[0148] In FIG. 9, n N-channel MOS transistors Q₄₀ to Q₄₄ are connectedin cascade to configure the booster circuit having n stages. Substrateportions of the respective transistors Q₄₀ to Q₄₄ are electricallyinsulated from one another, and also the substrate portions and gateterminals are connected to respective source terminals N₄₀ to N₄₄. Then,the clock signal φ_(A) or φ_(B) which is the same as that shown in FIG.8 is inputted to the terminals N₄₀ to N₄₄ through capacitors C₄₀ to C₄₄,respectively.

[0149] In the booster circuit according to the present embodiment, thepower supply voltage Vdd is inputted as an input signal from a sourceterminal N₄₇ of an N-channel MOS transistor Q₄₅ to the terminal N₄₀, andalso the output voltage V_(POUT) is outputted as an output signal froman output terminal N₄₆ through the N-channel MOS transistor Q₄₄.

[0150]FIG. 10 shows a device structure of the transistors Q₄₀ to Q₄₄according to the present embodiment.

[0151] In FIG. 10, P type well regions 51 are formed in an N typesemiconductor substrate 50, and in each of the P type well regions 51, apolycrystalline silicon layer 56 which is formed on the substrateportion of the well region 11 with a gate oxide film 55 disposedtherebetween is provided as a gate electrode, and also an N⁺ typeimpurity diffusion layer 52 is provided as a source/drain region. Insuch a manner, the MOS transistor is formed.

[0152] The N⁺ type impurity diffusion layer 52 of the source side ofeach of the transistors is electrically connected to the P type wellregion 51, in which the transistor is formed, through the P⁺ typeimpurity diffusion layer 54, and the source of the transistor in thepreceding stage is connected to the drain of the transistor in thesubsequent stage.

[0153] As a result, the potential at the P type well region of thesubstrate portion of each of the transistors is fixed to the sourcepotential of each of the transistors, and hence the substrate effect canbe effectively prevented from occurring.

[0154] In addition, the PN junction is formed between the N⁺ impuritydiffusion layer 52 of the drain side and the P type well region 51 ofeach of the transistors. When in the operation, the PN junction isbiased in the forward direction, the potential at the substrate portionof each of the transistors is fixed to the forward bias voltage acrossthe PN junction. In such a manner, the substrate effect can beeffectively prevented from occurring.

[0155] As described above, in the semiconductor booster circuitaccording to the third embodiment of the present invention, thesubstrate portions of the MOS transistors are electrically insulatedfrom one another, and also the substrate portions are electricallyconnected to the source terminals of the MOS transistors, respectively,whereby it is possible to prevent the increase of the threshold voltageVt due to the substrate effect. Therefore, it is possible to obtain theoutput voltage V_(POUT) proportional to the number n of stages of thesemiconductor booster circuit.

[0156] In addition, with respect to the device structure, as shown inFIG. 10, the P type well regions 51 in which the transistors Q₄₀ to Q₄₄are respectively formed are formed independently of each other and alsothe P⁺ type impurity diffusion region of each of the P type well regionsis electrically connected to the N⁺ type impurity diffusion region 52 ofthe source side of each of the transistors Q₄₀ to Q₄₄. Therefore, inparticular, the number of manufacturing processes is not increased atall.

[0157] In addition, the substrate portions of the transistors Q₄₀ to Q₄₄are electrically connected to the source terminals N₄₀ to N₄₄,respectively, whereby the PN junction which is formed in the boundarybetween the drain and the substrate portion is connected in parallelbetween the source and the drain of each of the transistors Q₄₀ to Q₄₄.Then, when transferring the electric charges from the preceding stage tothe subsequent stage in the booster circuit, the PN junction is switchedto the on state, whereby the potential at the substrate portion of eachof the transistors Q₄₀ to Q₄₄ can be fixed to the potential differencecorresponding to the forward bias voltage V_(F) (normally, about 0.7V)across the PN junction. Thus, it is possible to suppress the influenceof the substrate effect.

[0158] In the semiconductor booster circuits according to the second andthird embodiments of the present invention, the forward junction biasvoltage V_(F) can be employed instead of the threshold voltage Vt in theabove-mentioned expressions (1) and (2). In particular, in the casewhere the threshold voltage Vt is larger than the forward junction biasvoltage V_(F), since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage in the boostercircuit is reduced, it is possible to improve the boosting capability ofthe booster circuit. That is, the voltage drop when the electric chargesare transferred to the subsequent stage depends on the smaller one ofthe threshold voltage Vt and the forward junction bias voltage V_(F).

[0159] For example, in the case where the power supply voltage Vdd is2.5V and the number n of stages of the booster circuit is 20, assumingthat the capacitance ratio C/(C+Cs) is 0.9, the absolute value of thethreshold voltage |Vt| is 0.6V, the load current I_(OUT) in the outputstage is 0A, and the forward junction bias voltage V_(F) across the PNjunction is 0.7V, only 20V can be obtained as the output voltageV_(POUT) in the conventional booster circuit. But in the booster circuitaccording to the third embodiment of the present invention, about 33Vcan be obtained as the output voltage V_(POUT).

[0160] In addition, for example, in the case where the power supplyvoltage Vdd is 2.0V, assuming that the capacitance ratio C/(C+Cs) is0.9, the absolute value of the threshold voltage |Vt| is 0.6V, the loadcurrent I_(OUT) in the output stage is 0A, and the forward junction biasvoltage V_(F) across the PN junction is 0.7V, only 12V can be obtainedas the output voltage V_(POUT) in the convention booster circuit, evenwhen the number n of stages of the booster circuit is 50. But in thebooster circuit according to the third embodiment of the presentinvention, when the number n of stages of the booster circuit is 20,about 23V can be obtained as the output voltage V_(POUT), and also whenthe number n of stages of the booster circuit is 50, about 56V can beobtained.

[0161] In the semiconductor booster circuits according to the second andthird embodiments of the present invention, assuming that the forwardjunction bias voltage V_(F) across the PN junction is 0.7V, and thecapacitance ratio C/(C+Cs) is 0.9, the lower limit of the boostablepower supply voltage Vdd is about 0.8V.

[0162] In the above, the description has been given with respect to thefirst, second and third embodiments of the present invention since inthe booster circuit according to the first embodiment, the voltage dropwhen transferring the electric charges to the subsequent stage can bemade substantially zero, and hence, the booster circuit according to thefirst embodiment has the larger boosting capability as compared with thebooster circuits according to the second and third embodiments. Inparticular, in the power supply voltage Vdd of about 0.8V to 2.0V, thedifference in the boosting capability between the booster circuitaccording to the first embodiment and the booster circuit according tothe second or third embodiment becomes remarkable large.

[0163] In particular, in the power supply voltage Vdd of about 0.8V to2.0V, when the desired output voltage is larger, the number n of stagesneeds to be increased in the booster circuits according to the secondand third embodiments due to the voltage drop when transferring theelectric charges to the subsequent stage. However, in the boostercircuit according to the first embodiment, this is not required. Forexample, in the case where the power supply voltage Vdd is 2.0V, thenumber n of stages of the booster circuit required for obtaining 23V asthe output voltage V_(POUT) is 20 in the booster circuits according tothe second and third embodiments, but only 12 in the booster circuitaccording to the first embodiment.

[0164] On the other hand, the booster circuit according to the second orthird embodiment is advantageous as compared with the booster circuitaccording to the first embodiment in that the circuit configuration issimpler and also only two kinds of clock signals are sufficient.

[0165] In any one of the above-mentioned embodiments, since thesubstrate portions of the MOS transistors are electrically insulatedfrom one another, and also the substrate portions are electricallyconnected to the source terminals of the MOS transistors, respectively,the substrate effect can be effectively prevented from occurring.Therefore, the high boosting capability can be obtained.

[0166] In addition, no complicated manufacturing process is especiallyrequired.

[0167] Further, in the case where the same boosting capability isobtained, the number of stages of the booster circuit can be furtherreduced as compared with the prior art.

[0168] Therefore, in the above-mentioned expression (1), the thresholdvoltage Vt can be regarded as zero, and therefore, as compared with theconventional booster circuit, the boosting operation can be moreefficiently performed. Thus, even in the case where the number n ofstages of the booster circuit, and the power supply voltage Vdd are theas as those of the conventional booster circuit, it is possible toobtain a larger output voltage V_(POUT) than that of the conventionalbooster circuit.

[0169] For example, in the case where the power supply voltage Vdd is2.5V, and the number n of stages of the booster circuit is 20, assumingthat the capacitance ratio C/(C+Cs) is 0.9, the absolute value of thethreshold voltage |Vt| is 0.6V, the load current I_(OUT) in the outputstage is zero, and the boosted voltage Vhh is 3.0V, only 20V can beobtained as the output voltage V_(POUT) in the conventional circuit, butin the booster circuit according to the present embodiment, about 47Vcan be obtained as the output voltage V_(POUT).

[0170] This means that in the case where the output voltage V_(POUT) isthe same, the booster circuit according to the present embodiment canprovide a larger load current I_(OUT) than that in the conventionalcircuit.

[0171] In addition, in the booster circuit according to the presentembodiment, as can be seen from FIG. 14, even with a low power supplyvoltage Vdd which can not be boosted by the conventional circuit, thedesired output voltage can be obtained.

[0172] For example, assuming that the capacitance ratio C/(C+Cs) is 0.9,the absolute value of the threshold voltage |Vt| is 0.6V, the loadcurrent I_(OUT) in the output stage is zero, and the boosted voltage Vhhis 3.0V, the power supply voltage Vdd needs to be set to 2.5V or more,in the conventional booster circuit, in order to obtain 20V as theoutput voltage V_(POUT), but only 1.5V is sufficient for the powersupply voltage Vdd in the booster circuit according to the presentembodiment.

[0173] According to the fourth embodiment, since the clock signal whichis used to render the MOS transistor constituting each of the stagesconductive is boosted so as to have a larger amplitude than the powersupply voltage Vdd, the desired output voltage can be obtained even inthe case where the power supply voltage is low.

[0174] In addition, in the case where the power supply voltage isconstant, a larger load current than that in the prior art can beobtained.

[0175] Furthermore, in the case where the same output voltage as that inthe prior art is to be obtained, the number of stages of the boostercircuit can be further reduced as compared with the prior art.

[0176] Next, the description will hereinbelow be given with respect to afifth embodiment of the present invention with reference to FIGS. 15 and16.

[0177] A circuit configuration shown in FIG. 15 is identical to that ofFIG. 1 except for the provision of bootstrap circuits BS₇₁ and BS₇₂illustrated in the lower half of the figure. Therefore, the operation ofthe booster circuit according to the fifth embodiment of the presentinvention is substantially the same as that of the booster circuitaccording to the first embodiment. That is, the configuration of thefirst and second stages which are consecutive in the booster circuit ofthe fifth embodiment is the same as that of FIG. 2. Then, when the clocksignals φ_(1A), φ_(1B), φ_(2A) and φ_(2B) are inputted according to thetiming diagram as shown in FIG. 16 in the booster circuit of FIG. 15,the state in change of the operation of each of the transistors of thebooster circuit as shown in FIG. 2 and the tendency in change of thepotentials at the nodes N_(A), N_(B), N_(C) and N_(D) are the same asthose in the first embodiment shown in FIGS. 5A to 5F and FIGS. 4A and4D. The only differences between the first embodiment and the fifthembodiment are as follows.

[0178] (a) For a period of time of (II) of FIG. 16, the potential at thegate terminal N_(C) of the transistor M₁ is dropped as shown in FIG. 4C.However, the voltage drop is equal to the power supply voltage Vdd inthe first embodiment, but is equal to the boosted voltage Vhh in thefifth embodiment.

[0179] (b) For a period of time of (III) of FIG. 16, the potential atthe gate terminal N_(C) of the transistor M₁ is raised as shown in FIG.4C. In this connection, the raised voltage is equal to the power supplyvoltage Vdd in the first embodiment, but is equal to the boosted voltageVhh in the fifth embodiment.

[0180] (c) For a period of time of (V) of FIG. 16, the potential at thegate terminal N_(E) of the transistor M₃ is dropped. In this connection,the voltage drop is equal to the power supply voltage Vdd in the firstembodiment, but is equal to the boosted voltage Vhh in the fifthembodiment.

[0181] (d) For a period of time of (VI) of FIG. 16, the potential at thegate terminal N_(E) of the transistor M₃ is raised. In this connection,the raised voltage is equal to the power supply voltage Vdd in the firstembodiment, but is equal to the boosted voltage Vhh in the fifthembodiment.

[0182] Next, the description will hereinbelow be given with respect tothe operation of the bootstrap circuit BS₇₁ with reference to FIGS. 15and 16.

[0183] Firstly, the level of the clock signal CLK₂ shown in FIG. 17 ischanged from 0V up to Vdd. At first, the potential of φ_(2A) is changedfrom 0V to Vdd−Vt (Vt is the threshold voltage of the transistor Q₈₄).The threshold voltage Vt of the transistor Q₈₄ is, for example, 0.1V.When Vdd=1V, and the clock signal CLK₂ is changed from 0V to 1V, theinitial potential of φ_(2A) becomes 0.7V (Vt of the transistor Q₈₄ israised by about 0.2V due to the back bias effect). At the same time, theinverter IV₈₅ performs the inversion operation at the time when thelevel of the input voltage φ_(2A) has exceeded the logical thresholdvoltage (normally, about Vdd/2), and also the potential at the node N₉₀is dropped from Vdd to 0V. As a result, the transistor Q₈₅ is turned on.

[0184] Next, on the basis of the function of both the inverter IV₈₄ andthe capacitor C₈₃, the potential at the node N₈₇ is changed from Vdddown to 0V after a

[0185] predetermined time delay from the clock signal CLK₂ and the nodeN₉₀. Therefore, although the transistor Q₈₆ is initially in theon-state, after a

[0186] predetermined time delay, the transistor Q₈₆ is turned off. Untila lapse of the predetermined time delay, both the transistors Q₈₅ andQ₈₆ are in the on state. In this connection, by setting theon-resistance of the transistor Q₈₆ to a value sufficiently smaller thanthe on-resistance of the transistor Q₈₅, the potential at the node N₈₈is maintained at about 0V until a lapse of the predetermined time delay.That is, after a lapse of the predetermined delay time, the potential atthe node N₈₈ is changed from about 0V to Vdd.

[0187] Next, at the same time the potential at the node N₈₈ is changedfrom about 0V to Vdd, the potential of the clock signal φ_(2A) goes to(2Vdd−Vt) on the basis of the function of the capacitor C₈₂. Thus, it ispossible to obtain the larger voltage than Vdd. For example, in the caseof Vdd=1V, the level of the clock signal φ_(2A) settles to 1.7V.

[0188] The above description also applies to the other bootstrap circuitBS₇₂.

[0189] Therefore, by inputting the clock signals CLK₂ and CLK₃ to thebootstrap circuits BS₇₁ and BS₇₃, respectively, it is possible to obtainthe clock signals φ_(2A) and φ_(2B) each having a larger amplitude thanthe power supply voltage Vdd.

[0190] The fifth embodiment offers basically the same effects as thoseof the first embodiment in that the high output voltage can be obtained.In addition, in the fifth embodiment, the level of each of the clocksignals φ_(2A) and φ_(2B) is boosted by the bootstrap circuit BS₇₁ orBS₇₂ to a larger amplitude than the power supply voltage Vdd, wherebythe gate voltage of each of the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . ,Q₉, which are connected in cascade, can be made higher than that in theprior art. Therefore, even if the threshold voltage Vt is increased dueto the substrate effect, the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉can be normally turned on, and hence it is possible to obtain the outputvoltage V_(POUT) which is increased in proportion to the number n ofstages of the semiconductor booster circuit.

[0191] The relationship between the number of stages of the boostercircuit and the output voltage is substantially the same as that in thefourth embodiment shown in FIG. 13.

[0192] In addition, in the semiconductor booster circuit according tothe present embodiment, the MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉are driven by the clock signals φ_(2A) and φ_(2B) which are respectivelyobtained by boosting the clock signals CLK₂ and CLK₃ to a largeramplitude than the power supply voltage Vdd, whereby the MOS transistorsQ₁, Q₃, Q₅, Q₇, . . . , Q₉ can be sufficiently turned on even with thevery low power supply voltage value (e.g., Vdd=0.7 to 1.0V).

[0193] In the present embodiment, the lowest power supply voltage whichcan be boosted is determined by the threshold voltage Vt of each of theP-channel MOS transistors, Q₁, Q₃, Q₅, Q₇, . . . , Q₉ constituting thebooster circuit. As in the first embodiment, in the case where theamplitude V_(φ2) of each of the clock signals φ_(2A) and φ_(2B) is equalto the power supply voltage Vdd, the voltage drop at the node N_(C) in aperiod of time of (II) shown in FIG. 4C does not reach the thresholdvoltage Vt (e.g., −0.6V) of each of the P-channel MOS transistors Q₁,Q₃, Q₅, Q₇, . . . , Q₉ if Vdd becomes

[0194] equal to or lower than 1V and hence the P-channel MOS transistorsQ₁, Q₃, Q₅, Q₇, . . . , Q₉ can not be sufficiently turned on. On theother hand, as in the fifth embodiment, the amplitude V_(φ2) of each ofthe clock signals φ_(2A) and φ_(2B) is boosted by the bootstrap circuitBS₁ or BS₂ to a larger amplitude than the power supply voltage Vdd,whereby the boosting operation can be stably performed even in the verylow power supply voltage value of Vdd=0.7 to 1.0V. In addition, sincethe P-channel MOS transistors Q₁, Q₃, Q₅, Q₇, . . . , Q₉ can besufficiently turned on, it is also possible to prevent the reduction ofthe boosting capability of the booster circuit.

[0195] Now, the description will hereinbelow be given with respect tothe relationship between the power supply voltage Vdd and the maximumoutput voltage V_(POUT) when making the number of stages of the boostercircuit infinite with reference to FIG. 14. In the case of theconventional booster circuit, even if Vdd becomes larger than Vto, therelationship has a characteristic as shown in the curve (c) of FIG. 14since Vt is increased due to the substrate effect with the increase ofthe output voltage V_(POUT). On the other hand, in the booster circuitof the present embodiment, in the case where the relation ofV_(φ1)=V_(φ2)=V_(φ)=Vdd is established, and also the parasitic capacitycan be disregarded, i.e., for example, the relation of C/(C+Cs)=1 isestablished, the boosting operation can be performed depending on onlythe number n of stages of the booster circuit if the desired voltageequal to or higher than Vdd=V_(φ)=Vto is obtained. However, actually,since the parasitic capacity can not be disregarded, e.g. C/(C+Cs) isabout 0.9, the boosting operation can not be performed when V=Vdd,unless Vdd is equal to or larger than 1.1, like the fourth embodiment.In addition in the MOS transistor, even if the gate to source voltageexceeds Vto slightly, the boosting capability of the booster circuit isslightly reduced since the source to drain resistance is large and hencethe booster circuit provides a characteristic as shown in the curve (b)of FIG. 14.

[0196] On the other hand, in the structure of the fifth embodiment,since V_(φ2) can be set to 1.7 Vdd for example, it is possible to supplya gate to source voltage by which the MOS transistor can be sufficientlyturned on even if the parasitic capacity is present. As a result, thefifth embodiment provides a characteristic as shown in the curve (a) ofFIG. 14.

[0197] Next, the description will hereinbelow be given with respect to asixth embodiment of the present invention with reference to FIGS. 17 and18.

[0198]FIG. 17 shows a configuration of a semiconductor booster circuitaccording to the sixth embodiment of the present invention.

[0199] As shown in FIG. 17, N-channel depletion type MOS transistorsM₁₀₁ to M₁₀₈ are connected in series between an input terminal N₁₂₀ andan output terminal to configure a booster circuit having four stages.That is, each pair of the transistors M₁₀₁ and M₁₀₂; M₁₀₃ and M₁₀₄; M₁₀₅and M₁₀₆; M₁₀₇ and M₁₀₈ constitute respective stages. Gate terminals ofthe transistors M₁₀₁ to M₁₀₈ are respectively connected to drainterminals (represented by nodes N₁₀₀ to N₁₀₇). Then, a clock signalφ_(A) which is shown in FIG. 20 is inputted through capacitors C₁₀₁,C₁₀₃, C₁₀₅ and C₁₀₇, respectively, to the drain terminals N₁₀₀, N₁₀₂,N₁₀₄ and N₁₀₆ and also a clock signal φ_(B) which is in opposite phasewith the clock signal φ_(A) is inputted through capacitors C₁₀₂, C₁₀₄,C₁₀₆ and C₁₀₈, respectively, to the drain terminals N₁₀₁, N₁₀₃, N₁₀₅ andN₁₀₇. In addition, both drain terminals and gate terminals of N-channelMOS transistor M₁₂₀ and M₁₂₁ are connected to the input terminal(represented by a node N₁₂₀), and substrate terminals thereof areconnected to a ground terminal (represented by a node N₁₂₁).

[0200] In addition, substrate terminals of the transistors M₁₀₁ to M₁₀₈are divided into two groups, as will be described later, i.e., the groupof the transistors M₁₀₁ to M₁₀₄ and the group of the transistors M₁₀₅ toM₁₀₈. In this connection, the substrate terminals of the transistorsM₁₀₁ to M₁₀₄ and the substrate terminals of the transistors M₁₀₅ to M₁₀₈are respectively connected to the drain terminal N₁₀₀ of the transistorM₁₀₁ and the drain terminal N₁₀₄ of the transistor M₁₀₅.

[0201] That is, the node N₁₀₀ is connected to the source terminal of thetransistor M₁₂₀, both the drain terminal and the gate terminal of thetransistor M₁₀₁, one terminal of the capacitor C₁₀₁ and the substrateterminals of the transistors M₁₀₁ to M₁₀₄. The node N₁₀₁ is connected tothe source terminal of the transistor M₁₂₁, both the drain terminal andthe gate terminal of the transistor M₁₀₂, the source terminal of thetransistor M₁₀₁ and one terminal of the capacitor C₁₀₂. The node N₁₀₂ isconnected to both the drain terminal and the gate terminal of thetransistor M₁₀₃, the source terminal of the transistor M₁₀₂ and oneterminal of the capacitor C₁₀₃. The node N₁₀₃ is connected to both thedrain terminal and the gate terminal of the transistor M₁₀₄, the sourceterminal of the transistor M₁₀₃ and one terminal of the capacitor C₁₀₄.The node N₁₀₄ is connected to both the drain terminal and the gateterminal of the transistor M₁₀₅, the source terminal of the transistorM₁₀₄, one terminal of the capacitor C₁₀₅ and the substrate terminals ofthe transistors M₁₀₅ to M₁₀₈. The node N₁₀₅ is connected to both thedrain terminal and the gate terminal of the transistor M₁₀₆, the sourceterminal of the transistor M₁₀₅ and one terminal of the capacitor C₁₀₆.The node N₁₀₆ is connected to both the drain terminal and the gateterminal of the transistor M₁₀₇, the source terminal of the transistorM₁₀₆ and one terminal of the capacitor C₁₀₇. In addition, the node N₁₀₇is connected to both the drain terminal and the gate terminal of thetransistor M₁₀₈, the source terminal of the transistor M₁₀₇ and oneterminal of the capacitor C₁₀₈. Further, the output terminal of thesemiconductor booster circuit is connected to the source terminal of thetransistor M₁₀₈.

[0202] In this configuration, the series-connected four stages aredivided into a group of two stages of the input side including thetransistors M₁₀₁ to M₁₀₄ and a group of two stages of the output sideincluding the transistors M₁₀₅ to M₁₀₈. Therefore, the substrateterminals of the transistors M₁₀₁ to M₁₀₈ are divided into the group ofsubstrate terminals of the transistors M₁₀₁ to M₁₀₄ and the group ofsubstrate terminals of the transistors M₁₀₅ to M₁₀₈. In this connection,the substrate terminals of the transistors M₁₀₁ to M₁₀₄ are connected tothe drain terminal N₁₀₀ of the transistor M₁₀₁ and the substrateterminals of the transistors M₁₀₅ to M₁₀₈ are connected to the drainterminal N₁₀₄ of the transistor M₁₀₅. Therefore, as compared with theconventional booster circuit shown in FIG. 26, a substrate bias voltageVbs of the transistors M₁₀₁ to M₁₀₇ in the booster circuit of thepresent embodiment is smaller than that of the transistors M₁ to M₇ inthe conventional booster circuit. As a result, the threshold voltage Vtof the transistors M₁₀₅ to M₁₀₈ in the booster circuit of the presentembodiment is lower than that of the transistors M₅ to M₈ in theconventional booster circuit. As a result, as compared with theconventional booster circuit, the boosting capability is furtherimproved in the booster circuit of the present embodiment so that thehigh output voltage is obtained, and also the number of stages requiredfor obtaining the same output voltage can be further reduced, ascompared with the conventional booster circuit. In addition, since thethreshold voltage Vt in each of the stages is lowered, the lower limitof the boostable power supply voltage Vdd becomes small, and hence thedrive with the low power supply voltage becomes possible.

[0203] Next, the description will hereinbelow be given with respect tothe device structure of the booster circuit shown in FIG. 17 withreference to FIG. 18.

[0204] As shown in FIG. 18, in an N type well region 402 which is formedin a P type semiconductor substrate 401, P type well regions 403, 404and 405 are respectively formed. P⁺ type impurity diffusion layer 406and N⁺ type impurity diffusion layers 409 and 410 are respectivelyformed in the P⁺ type well region 403, and also a polycrystallinesilicon film 421 as a gate electrode is formed above a channel regionbetween the N type impurity diffusion layers 409 and 410 as the drainand the source with an interposed gate oxide film (not shown), therebyconstituting the transistor M₁₂₀. In addition, a P⁺ type impuritydiffusion layer 407 and N⁺ type impurity diffusion layers 411 to 415 arerespectively formed in the P type well region 404, and alsopolycrystalline silicon films 422 to 425 as gate electrodes of thetransistors are formed above channel regions between N⁺ type impuritydiffusion layers 411 to 415 constituting the drains or the sources ofthe transistors with an intermediate gate oxide film (not shown),thereby constituting the four transistors M₁₀₁ to M₁₀₄. In addition, aP⁺ type impurity diffusion layer 408 and N⁺ type impurity diffusionlayers 416 to 420 are respectively formed in the P type well region, andalso polycrystalline silicon films 426 to 429 as gate electrodes of thetransistors are formed above channel regions between N⁺ type impuritydiffusion layers 416 to 420 constituting the drains or the sources ofthe transistors with an intermediate gate oxide film (not shown),thereby constituting the four transistors M₁₀₅ to M₁₀₈.

[0205] The polycrystalline silicon films 422 to 425 as the gateelectrodes of the transistors M₁₀₁ to M₁₀₄ are respectively connected tothe N⁺ type impurity diffusion layers 411 to 414, and thepolycrystalline silicon films 426 to 429 as the gate electrodes of thetransistors M₁₀₅ to M₁₀₈ are respectively connected to the N⁺ typeimpurity diffusion layers 416 to 419. In addition, the clock signalφ_(A) as shown in FIG. 4 is inputted through the capacitors C₁₀₁, C₁₀₃,C₁₀₅ and C₁₀₇, respectively, to the polycrystalline silicon films 422,424, 426 and 428 as the gate electrodes of the transistors M₁₀₁, M₁₀₃,M₁₀₅ and M₁₀₇ and the clock signal φ_(B) which is in opposite phase withthe clock signal φ_(A) is inputted through the capacitors C₁₀₂, C₁₀₄,C₁₀₆ and C₁₀₈, respectively to the polycrystalline silicon films 423,425, 427 and 429 as the gate electrodes of the transistors M₁₀₂, M₁₀₄,M₁₀₆ and M₁₀₈. In addition, both the N⁺ type impurity diffusion layer409 as the drain and the polycrystalline silicon film 421 as the gateelectrode of the transistor M₁₂₀ are connected to the power supplyterminal N₁₂₀. The P type well region 403 is connected to the groundterminal N₁₂₁ through the P⁺ type impurity diffusion layer 406, andhence the substrate potential of the transistor M₁₂₀ is equal to thepotential at the P type well region 403. In addition, the P type wellregion 404 is connected to both the N⁺ type impurity diffusion layer 410as the source of the transistor M₁₂₀ and the N⁺ type impurity diffusionlayer 411 as the drain of the transistor M₁₀₁ through the P⁺ typeimpurity diffusion layer 407, and hence the substrate potential of eachof the transistors M₁₀₁ to M₁₀₄ is equal to the potential at the P typewell region 404. Further, the P type well region 405 is connected toboth the N⁺ type impurity diffusion layer 415 as the source of thetransistor M₁₀₄ and the N⁺ type impurity diffusion layer 416 as thedrain of the transistor M₁₀₅ through the P⁺ type impurity diffusionlayer 408, and hence the substrate potential of each of the transistorsM₁₀₅ to M₁₀₈ is equal to the potential at the P type well region 405.

[0206] Although in the embodiment described above, the substrateportions of the eight transistors M₁₀₁ to M₁₀₈ constituting the boostercircuit are divided into two groups, the number of groups is not limitedthereto. For example, the substrate portions are divided by every stage,and thus the four groups may be formed. But, if each division is toosmall, although the boosting efficiency is improved, there arises aproblem that the integration of the elements can not be increased.Incidentally, although the above-mentioned embodiment has the circuitconfiguration having the four stages, it is to be understood that thenumber of stages is not limited thereto.

[0207] Next, the description will hereinbelow be given with respect to aseventh embodiment of the present invention with reference to FIGS. 19and 21.

[0208] As shown in FIG. 19, four circuit blocks PCH₀₁ to PCH₀₄ areconnected in cascade to configure the semiconductor booster circuitaccording to the seventh embodiment of the present invention. Each ofthe circuit blocks PCH₀₁ to PCH₀₄ is configured by connecting P-channelMOS transistors P₂₀₁ and P₂₀₂ in series with each other. Now, to a drainterminal N₂₀₁ of the transistor P₂₀₁, a clock signal φ_(1A) which isshown in FIG. 21 is inputted through a capacitor C₂₀₁. To a gateterminal N₂₀₃ of the transistor P₂₀₁, a clock signal φ_(2A) shown inFIG. 21 is inputted through a capacitor C₂₀₂. To a drain terminal N₂₀₂of the transistor P₂₀₂, a clock signal φ_(1B) is inputted through acapacitor C₂₀₃. In addition, to a gate terminal N₂₀₅ of the transistorP₂₀₂, a clock signal φ_(2B) is inputted through a capacitor C₂₀₄.Further, a P-channel MOS transistor P₂₀₃ is connected between the sourceterminal N₂₀₂ and the gate terminal N₂₀₃ of the transistor P₂₀₁, and thegate terminal of the transistor P₂₀₃ is connected to the drain terminalN₂₀₁ of the transistor P₂₀₁. In addition, a P-channel MOS transistorP₂₀₄ is connected between the source terminal N₂₀₄ and the gate terminalN₂₀₅ of the transistor P₂₀₂, and the gate terminal of the transistorP₂₀₄ is connected to the drain terminal N₂₀₂ of the transistor P₂₀₂.

[0209] In addition, drain terminals and gate terminals of N-channeldepletion type MOS transistors M₂₂₀ and M₂₂₁ are respectively connectedto a power supply terminal N₂₂₀, substrate terminals thereof areconnected to a ground terminal N₂₂₁, and source terminals thereof arerespectively connected to the drain terminals N₂₀₁ and N₂₀₂ of thetransistors P₂₀₁ and P₂₀₂ in the circuit block PCH₀₁. Incidentally,instead of the N-channel depletion type MOS transistors M₂₂₀ and M₂₂₁,N-channel enhancement type MOS transistors may also be used.

[0210] Substrate terminals of the four transistors P₂₀₁ to P₂₀₄ in thecircuit blocks PCH₀₁ and PCH₀₂ are connected to a substrate terminalSUB₁ formed of a common N type well region, and the substrate terminalSUB₁ is connected to a source terminal (not shown) of the transistorP₂₀₄ in the circuit block PCH₀₂. On the other hand, substrate terminalsof four transistors P₂₀₁ to P₂₀₄ in the circuit blocks PCE₀₃ and PC₀₄are connected to a substrate terminals SUB₂ formed of a common N typewell region, and the substrate terminal SUB₂ is connected to the sourceterminal (not shown) of the transistor P₂₀₄ in the circuit block PC₀₄.Incidentally, the substrate terminals SUB₁ and SUB₂ are electricallyinsulated from each other.

[0211] The source terminal N₂₀₄ of the transistor P₂₀₂ in the circuitblock PC₀₁ is connected to the drain terminal N₂₀₁ of the transistorP₂₀₁ in the circuit block PCE₀₂, the source terminal N₂₀₄ of thetransistor P₂₀₂ in the circuit block PCH₀₂ is connected to the drainterminal N₂₀₁ of the transistor P₂₀₁ in the circuit block PCH₀₃, and thesource terminal N₂₀₄ of the transistor P₂₀₂ in the circuit block PCH₀₃is connected to the drain terminal N₂₀₁ of the transistor P₂₀₁ in thecircuit block PCH₀₄ so that the four circuit blocks PCH₀₁ to PCH₀₄ areconnected in cascade. In addition, the source terminal of the transistorP₂₀₂ in the circuit block PCH₀₄ is connected to an output terminal toprovide the output voltage V_(POUT).

[0212] Next, the description will hereinbelow be given with respect tothe operation of the semiconductor booster circuit according to theseventh embodiment of the present invention. Incidentally, in thefollowing description, it is meant by “smaller than the thresholdvoltage” that the potential at the drain or the source is lower thanthat at the gate, or the potential at the source or the drain is higherthan that at the gate, but the difference therebetween is smaller thanthe threshold voltage. By “larger than the threshold voltage”, it ismeant that the potential at the source or the drain is higher than thatat the gate and additionally the difference therebetween is larger thanthe threshold voltage.

[0213] Firstly, for a period of time of (I) of FIG. 21, the level of theclock signal φ_(1A) is the low potential (“L”), and the level of each ofthe clock signals φ_(2A), φ_(1B) and φ_(2B) are the high potential(“H”). Thus, a current is caused to flow from the power supply terminalN₂₂₀ shown in FIG. 19 to the drain terminal N₂₀₁ of the transistor P₂₀₁through the transistor M₂₂₀, and hence the electric charges areaccumulated in the capacitor C₂₀₁. The potential at the drain terminalN₂₀₂ of the transistor P₂₀₂ is higher than its previous potentialexisting when the level of the clock signal 1B was previously “L” byV_(o) C/(C+Cs)(V_(φ) is the amplitude of each of the clock signalsφ_(1A) and φ_(1B)) shown in the above-mentioned expression (1). Thus, ifthe relation in magnitude between the potential at the drain terminalN₂₀₁ of the transistor P₂₀₁ and the potential at the drain terminal N₂₀₂of the transistor P₂₀₂ becomes larger than the threshold value of thetransistor P₂₀₃, the transistor P₂₀₃ is turned on, and hence theconduction is established between the gate terminal N₂₀₃ of thetransistor P₂₀₁ and the drain terminal N₂₀₂ of the transistor P₂₀₂. Atthis time, since the potential between the gate terminal N₂₀₃ and thedrain terminal N₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁is lower than the threshold voltage of the transistor P₂₀₁, thetransistor P₂₀₁ is turned off. In addition, both the transistors P₂₀₂and P₂₀₄ are turned off since the potential between the gate terminaland the drain terminal or the source terminal is lower than thethreshold voltage.

[0214] Next, when the operation proceeds from a period of time of (I) toa period of time of (II), the level of each of the clock signals φ_(2A)and φ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “L” to “H” and the level of the clock signal φ_(1B) ischanged from “H” to “L”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “L” to “H”, and also thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “H” to “L”. Then, at the time point when the potential between thegate terminal N₂₀₁ and the drain terminal N₂₀₂ or the source terminalN₂₀₃ of the transistor P₂₀₃ has become lower than the threshold voltageof the transistor P₂₀₃, the transistor P₂₀₃ is switched from the onstate to the off state. In addition, at the time point when thepotential between the gate terminal N₂₀₂ and the drain terminal N₂₀₄ orthe source terminal N₂₀₅ of the transistor P₂₀₄ has become larger thanthe threshold voltage of the transistor P₂₀₄, the transistor P₂₀₄ isswitched from the off state to the on state, and also the conduction isestablished between the drain terminal N₂₀₄ and the source terminal N₂₀₅of the transistor P₂₀₄.

[0215] Next, when the operation proceeds from a period of time of (II)to a period of time of (III), the level of each of the clock signalsφ_(1A) and φ_(2B) remains “H”, and the level of the clock signal φ_(1B)remains “L”, and also the level of the clock signal φ_(2A) is changedfrom “H” to “L”. Therefore, the potential at the gate terminal N₂₀₃ ofthe transistor P₂₀₁ is changed from “H” to “L”, and hence at the timepoint when the potential

[0216] between the gate terminal N₂₀₃ and the drain terminal N₂₀₁ or thesource terminal N₂₀₂ of the transistor P₂₀₁ has become larger than thethreshold voltage of the transistor P₂₀₁, the transistor P₂₀₁ isswitched from he off state to the on state, a current is caused to flowfrom the drain terminal N₂₀₁ of the transistor P₂₀₁ to the drainterminal N₂₀₂ of the transistor P₂₀₂, and the potential at the drainterminal N₂₀₂ of the transistor P₂₀₂ is raised.

[0217] Next, when the operation proceeds from a period of time of (III)to a period of time of (IV), the level of each of the clock signalsφ_(1A) and φ_(2B) remains “H”, and the level of the clock signal φ_(1B)remains “L”, and also the level of the clock signal φ_(2A) is changedfrom “L” to “E”. Therefore, the potential at the gate terminal N₂₀₃ ofthe transistor P₂₀₁ is changed from “L” to “H”, and also the transistorP₂₀₁ is switched from the on state to the off state.

[0218] Next, when the operation proceeds from a period of time of (IV)to a period of time of (V), the level of each of the clock signalsφ_(2A) and φ_(2B) remains “H”, and also the level of the clock signalφ_(1A) is changed from “H” to “L”, and the level of the clock signalφ_(1B) is changed from “L” to “H”. Therefore, the potential at the gateterminal N₂₀₁ of the transistor P₂₀₃ is changed from “H” to “L”, and thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “L” to “H”, and at the time point when the potential between thegate terminal N₂₀₁ and the drain terminal N₂₀₂ or the source terminalN₂₀₃ of the transistor P₂₀₃ has become larger than the threshold voltageof the transistor P₂₀₃, the transistor P₂₀₃ is switched from the offstate to the on state, and the conduction is established between thedrain terminal N₂₀₂ and the source terminal N₂₀₃ of the transistor P₂₀₃.In addition, at the time point when the potential

[0219] between the gate terminal N₂₀₂ and the drain terminal N₂₀₄ or thesource terminal N₂₀₅ of the transistor P₂₀₄ has become smaller than thethreshold voltage of the transistor P₂₀₄, the transistor P₂₀₄ isswitched from the on state to the off state.

[0220] Next, when the operation proceeds from a period of time of (V) toa period of time of (VI), the level of each of the clock signals φ_(2A)and φ_(1B) remains “H”, the level of the clock signal φ_(1A) remains“L”, and the level of the clock signal φ_(2A) is changed from “H” to“L”. Therefore, the potential at the gate terminal N₂₀₅ of thetransistor P₂₀₂ is changed from “H” to “L”, and hence at the time pointwhen the potential between the gate terminal N₂₀₅ and the drain terminalN₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ has becomelarger than the threshold voltage of the transistor P_(2O2), thetransistor P₂₀₂ is changed from the off state to the on state, a currentis caused to flow from the drain terminal N₂₀₂ to the source terminalN₂₀₄ of the transistor P₂₀₂, and the potential at the source terminalN₂₀₄ of the transistor P₂₀₂ is raised.

[0221] Next, when the operation proceeds from a period of time of (VI)to a period of time of (VII), the level of each of the clock signalsφ_(2A) and φ_(1B) remains “E”, and also the level of the clock signalφ_(1A) remains “L”, and the level of the clock signal φ_(2B) is changedfrom “L” to “E”. Therefore, the potential at the gate terminal N₂₀₅ ofthe transistor P₂₀₂ is changed from “L” to “E”, and hence at the timepoint when the potential relation between the gate terminal N₂₀₅ and thedrain terminal N₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂has become smaller than the threshold voltage of the transistor P₂₀₂,the transistor P₂₀₂ is switched from the on state to the off state.

[0222] In the above-mentioned operation, with respect to the transistorsP₂₀₁ and P₂₀₃ and the capacitors C₂₀₁ and C₂₀₂ for example, when thepotential at the node N₂₀₁ is “E” and the potential at each of the nodesN₂₀₂ and N₂₀₃ is “L” (for a period of time of (III)), the transistorP₂₀₁ is turned on, a current is caused to flow from the node N₂₀₁ to thenode N₂₀₂, and the potential at the node N₂₀₂ is further raised ascompared with its potential at the time before the transistor P₂₀₁ isturned on. Subsequently, when the level of the clock signal φ_(1A) goesto “L”, the level of the clock signal φ_(1B) goes “H”, and also thepotential at the node N₂₀₁ goes to “L” and the potential at the nodeN₂₀₂ goes to “H” (for a period of time of (V)), the transistor P₂₀₃ isturned on, and the node N₂₀₂ becomes conductive with the node N₂₀₃.Therefore, the potential difference between the source and the gate ofthe transistor P₂₀₁ becomes zero. At this time, although the potentialat the node N₂₀₁ becomes lower than that at the node N₂₀₂, no current iscaused to flow between the nodes N₂₀₂ and N₂₀₁ since the transistor P₂₀₁is turned off. In addition, the potential at the node N₂₀₂ becomeshigher than the potential existing when the transistor P₂₀₁ is in the onstate by about Vφ·C/(C+Cs) as shown in the expression (1), and thereforethe potential at the node N₂₀₂ becomes higher than the potentialexisting when the “H” state has been obtained.

[0223] The above-mentioned operation is also applicable to the circuitblocks PCH₀₂ to PCE₀₄, and hence the output potential of the circuitblock located at preceding stages or closer to the output terminalbecomes higher in the positive direction. That is, the semiconductorbooster circuit according to the seventh embodiment is the positive highvoltage generating circuit employing the P-channel MOS transistors.

[0224] Incidentally, in the semiconductor booster circuit according tothe seventh embodiment, for example, since the potential at thesubstrate terminal SUB₁ is higher than the potential at the sources ordrains of the transistors P₂₀₁ and P₂₀₂, the absolute value of thethreshold voltage is increased due to the substrate effect, and henceboth the transistors P₂₀₁ and P₂₀₂ are difficult to be turned on, orthere is a possibility that the on-current becomes small. However, thewhole substrate potentials are divided into the two potentials, i.e.,the potential at SUB₁ and the potential at SUB₂, whereby the increase ofthe threshold voltage due to the substrate bias effect is reduced. Ifthe substrate potentials are divided into four blocks and the potentialof each block is controlled, the integration becomes poor but theincrease of the threshold voltage due to the substrate bias effect canbe further reduced.

[0225] In the semiconductor booster circuit according to the seventhembodiment, since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage can be madesubstantially zero, the larger boosting capability is obtained ascompared with the sixth embodiment. In particular, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the difference inboosting capability between the sixth embodiment and the seventhembodiment becomes remarkably large. For example, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the number n of stagesof the booster circuit required for obtaining a desired output voltageneeds to be greatly increased in the booster circuit of the sixthembodiment due to the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage, but in thebooster circuit of the seventh embodiment, it is not required at all.For example, in the case where the power supply voltage Vdd is 2.0V, inthe sixth embodiment, the number of stages of the booster circuitrequired for obtaining the output voltage V_(POUT) of 23V is 20 whereasin the booster circuit of the seventh embodiment, the required number ofstages is only 12.

[0226] On the other hand, the booster circuit of the sixth embodiment isadvantageous as compared with the booster circuit of the seventhembodiment in that the configuration is simpler and also only two kindsof clock signals are required.

[0227] Incidentally, it is to be understood that in the above-mentionedembodiments, the various changes may be made. For example, the number ofstages of the booster circuit is not limited to four in theabove-mentioned embodiment, and hence it may be set to any valuedetermined in accordance with the voltage to be boosted, the circuitscale and the like. In addition, the N-channel depletion type MOStransistors M₁₀₁ to M₁₀₈ are exemplarily employed as the transistorsconstituting the booster circuit in the sixth embodiment and also theP-channel MOS transistors P₂₀₁ to P_(2O4) are exemplarily employed asthe transistors constituting the booster circuit in the seventhembodiment. However, as for those transistors, other transistors such asN-channel enhancement type MOS transistors may also be employed. Forexample, the N-channel MOS transistors M₁₀₁ to M₁₀₈ in the sixthembodiment may be substituted by P-channel MOS transistors which areformed in the N type well region, and also the power supply terminalN₁₂₀ may be grounded to provide the negative high voltage generatingcircuit. In addition, the P-channel MOS transistors P₂₀₁ to P₂₀₄ in theseventh embodiment may be substituted by N-channel MOS transistors whichare formed in the P type well region to provide the negative highvoltage generating circuit.

[0228] In the sixth and seventh embodiments, the substrate terminals ofthe MOS transistors constituting the booster circuit are divided intothe necessary groups, and also are controlled to the differentpotentials for the groups, whereby it is possible to prevent thesubstrate bias effect from occurring. Therefore, the high boostingcapability can be obtained and also the increase of the circuit area canbe kept to a minimum. Incidentally, the substrate terminals SUB₁ andSUB₂ are electrically insulated from each other.

[0229] The source terminal N₂₀₄ of the transistor P₂₀₂ in the circuitblock PCH₀₁ is connected to the drain terminal N₂₀₁ of the transistorP₂₀₁ in the circuit block PCH₀₂, the source terminal N₂₀₄ of thetransistor P₂₀₂ in the circuit block PCH₀₂ is connected to the drainterminal N₂₀₁ of the transistor P₂₀₁ in the circuit block PCH₀₃, and thesource terminal N₂₀₄ of the transistor P₂₀₂ in the circuit block PCH₀₃is connected to the drain terminal N₂₀₁ of the transistor P₂₀₁ in thecircuit block PCH₀₄ so that the four circuit blocks PCH₀₁ to PCH₀₄ areconnected in cascade. In addition, the source terminal of the transistorP₂₀₂ in the circuit block PCH₀₄ is connected to an output terminal tooutput the output voltage V_(POUT).

[0230] Next, the description will hereinbelow be given with respect tothe operation of the semiconductor booster circuit according to theseventh embodiment of the present invention. Incidentally, in thefollowing description, it is meant by “smaller than the thresholdvoltage” that the potential at the drain or the source is lower thanthat at the gate, or the potential at the source or the drain is higherthan that at the gate, but the difference therebetween is smaller thanthe threshold voltage. By “larger than the threshold voltage”, it ismeant that the potential at the source or the drain is higher than thatat the gate and additionally the difference therebetween is larger thanthe threshold voltage.

[0231] Firstly, for a period of time of (I) of FIG. 21, the level of theclock signal φ_(1A) is the low potential (“L”), and the level of each ofthe clock signals φ_(2A), φ_(1B) and φ_(2B) are the high potential(“H”). Thus, a current is caused to flow from the power supply terminalN₂₂₀ shown in FIG. 19 to the drain terminal N₂₀₁ of the transistor P₂₀₁through the transistor M₂₂₀, and hence the electric charges areaccumulated in the capacitor C₂₀₁. The potential at the drain terminalN₂₀₂ of the transistor P₂₀₂ is higher than its previous potentialexisting when the level of the clock signal 1B was previously “L” byV_(φ) C/(C+Cs)(V_(φ) is the amplitude of each of the clock signalsφ_(1A) and φ_(1B)) shown in the above-mentioned expression (1). Thus, ifthe relation in magnitude between the potential at the drain terminalN₂₀₁ of the transistor P₂₀₁ and the potential at the drain terminal N₂₀₂of the transistor P₂₀₂ becomes larger than the threshold value of thetransistor P₂₀₃, the transistor P₂₀₃ is turned on, and hence theconduction is established between the gate terminal N₂₀₃ of thetransistor P₂₀₁ and the drain terminal N₂₀₂ of the transistor P₂₀₂. Atthis time, since the potential relation between the gate terminal N₂₀₃and the drain terminal N₂₀₁ or the source terminal N₂₀₂ of thetransistor P₂₀₁ is lower than the threshold voltage of the transistorP₂₀₁, the transistor P₂₀₁ is turned off. In addition, both thetransistors P₂₀₂ and P₂₀₄ are turned off since the potential relationbetween the gate terminal and the drain terminal or the source terminalis lower than the threshold voltage.

[0232] Next, when the operation proceeds from a period of time of (I) toa period of time of (II), the level of each of the clock signals φ_(2A)and φ_(2B) remains “H”, and also the level of the clock signal φ_(1A) ischanged from “L” to “H” and the level of the clock signal φ_(1B) ischanged from “H” to “L”. Therefore, the potential at the gate terminalN₂₀₁ of the transistor P₂₀₃ is changed from “L” to “H”, and also thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “H” to “L”. Then, at the time point when the potential relationbetween the gate terminal N₂₀₁ and the drain terminal N₂₀₂ or the sourceterminal N₂₀₃ of the transistor P₂₀₃ has become lower than the thresholdvoltage of the transistor P₂₀₃, the transistor P₂₀₃ is switched from theon state to the off state. In addition, at the time point when thepotential relation between the gate terminal N₂₀₂ and the drain terminalN₂₀₄ or the source terminal N₂₀₅ of the transistor P₂₀₄ has becomelarger than the threshold voltage of the transistor P₂₀₄, the transistorP₂₀₄ is switched from the off state to the on state, and also theconduction is established between the drain terminal N₂₀₄ and the sourceterminal N₂₀₅ of the transistor P₂₀₄.

[0233] Next, when the operation proceeds from a period of time of (II)to a period of time of (III), the level of each of the clock signalsφ_(1A) and φ_(2B) remains “H”, and the level of the clock signal φ_(1B)remains “L”, and also the level of the clock signal φ_(2A) is changedfrom “H” to “L”. Therefore, the potential at the gate terminal N₂₀₃ ofthe transistor P₂₀₁ is changed from “H” to “L”, and hence at the timepoint when the potential relation between the gate terminal N₂₀₃ and thedrain terminal N₂₀₁ or the source terminal N₂₀₂ of the transistor P₂₀₁has become larger than the threshold voltage of the transistor P₂₀₁, thetransistor P₂₀₁ is switched from the off state to the on state, acurrent is caused to flow from the drain terminal N₂₀₁ of the transistorP₂₀₁ to the drain terminal N₂₀₂ of the transistor P₂₀₂, and thepotential at the drain terminal N₂₀₂ of the transistor P₂₀₂ is raised.

[0234] Next, when the operation proceeds from a period of time of (III)to a period of time of (IV), the level of each of the clock signalsφ_(1A) and φ_(2B) remains “H”, and the level of the clock signal φ_(1B)remains “L”, and also the level of the clock signal φ_(2A) is changedfrom “L” to “H”. Therefore, the potential at the gate terminal N₂₀₃ ofthe transistor P₂₀₁ is changed from “L” to “H”, and also the transistorP₂₀₁ is switched from the on state to the off state.

[0235] Next, when the operation proceeds from a period of time of (IV)to a period of time of (V), the level of each of the clock signalsφ_(2A) and φ_(2B) remains “H”, and also the level of the clock signalφ_(1A) is changed from “H” to “L”, and the level of the clock signalφ_(1B) is changed from “L” to “H”. Therefore, the potential at the gateterminal N₂₀₁ of the transistor P₂₀₃ is changed from “H” to “L”, and thepotential at the gate terminal N₂₀₂ of the transistor P₂₀₄ is changedfrom “L” to “H”, and at the time point when the potential relationbetween the gate terminal N₂₀₁ and the drain terminal N₂₀₂ or the sourceterminal N₂₀₃ of the transistor P₂₀₃ has become larger than thethreshold voltage of the transistor P₂₀₃, the transistor P₂₀₃ isswitched from the off state to the on state, and the conduction isestablished between the drain terminal N₂₀₂ and the source terminal N₂₀₃of the transistor P₂₀₃. In addition, at the time point when thepotential relation between the gate terminal N₂₀₂ and the drain terminalN₂₀₄ or the source terminal N₂₀₅ of the transistor P₂₀₄ has becomesmaller than the threshold voltage of the transistor P₂₀₄, thetransistor P₂₀₄ is switched from the on state to the off state.

[0236] Next, when the operation proceeds from a period of time of (V) toa period of time of (VI), the level of each of the clock signals φ2A andφ_(1B) remains “H”, the level of the clock signal φ_(1A) remains “L”,and the level of the clock signal φ_(2A) is changed from “H” to “L”.Therefore, the potential at the gate terminal N₂₀₅ of the transistorP₂₀₂ is changed from “H” to “L”, and hence at the time point when thepotential relation between the gate terminal N₂₀₅ and the drain terminalN₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂ has becomelarger than the threshold voltage of the transistor P₂₀₂, the transistorP₂₀₂ is changed from the off state to the on state, a current is causedto flow from the drain terminal N₂₀₂ to the source terminal N₂₀₄ of thetransistor P₂₀₂, and the potential at the source terminal N₂₀₄ of thetransistor P₂₀₂ is raised.

[0237] Next, when the operation proceeds from a period of time of (VI)to a period of time of (VII), the level of each of the clock signalsφ_(2A) and φ_(1B) remains “H”, and also the level of the clock signalφ_(1A) remains “L”, and the level of the clock signal φ_(2B) is changedfrom “L” to “H”. Therefore, the potential at the gate terminal N₂₀₅ ofthe transistor P₂₀₂ is changed from “L” to “H”, and hence at the timepoint when the potential relation between the gate terminal N₂₀₅ and thedrain terminal N₂₀₂ or the source terminal N₂₀₄ of the transistor P₂₀₂has become smaller than the threshold voltage of the transistor P₂₀₂,the transistor P₂₀₂ is switched from the on state to the off state.

[0238] In the above-mentioned operation, with respect to the transistorsP₂₀₁ and P₂₀₃ and the capacitors C₂₀₁ and C₂₀₂ for example, when thepotential at the node N₂₀₁ is “H” and the potential at each of the nodesN₂₀₂ and N₂₀₃ is “L” (for a period of time of (III)), the transistorP₂₀₁ is turned on, a current is caused to flow from the node N₂₀₁ to thenode N₂₀₂, and hence the potential at the node N₂₀₂ is further raised ascompared with its potential at the time before the transistor P₂₀₁ isturned on. Subsequently, when the level of the clock signal φ_(1A) goesto “L”, the level of the clock signal φ_(1B) goes to “H”, and also thepotential at the node N₂₀₁ goes to “L” and the potential at the nodeN₂₀₂ goes to “H” (for a period of time of (V)), the transistor P₂₀₃ isturn on, and the node N₂₀₂ becomes conductive with the node N₂₀₃.Therefore, the potential difference between the source and the gate ofthe transistor P₂₀₁ becomes zero. At this time, although the potentialat the node N₂₀₁ becomes lower than that at the node N₂₀₂, no current iscaused to flow between the nodes N₂₀₂ and N₂₀₁ since the transistor P₂₀₁is turned off. In addition, the potential at the node N₂₀₂ becomeshigher than the potential existing when the transistor P₂₀₁ is in the onstate by about Vφ·C/(C+Cs) as shown in the expression (1), and thereforethe potential at the node N₂₀₂ becomes higher than the potentialexisting when the “H” state has been obtained.

[0239] The above-mentioned operation is also applied to the circuitblocks PCH₀₂ to PCH₀₄, and hence the output potential of the circuitblock located more backward stage or closer to the output terminalbecomes higher in the positive direction. That is, the semiconductorbooster circuit according to the seventh embodiment is the positive highvoltage generating circuit employing the P-channel MOS transistors.

[0240] Incidentally, in the semiconductor booster circuit according tothe seventh embodiment, for example, since the potential at thesubstrate terminal SUB₁ is higher than the potential at the sources ordrains of the transistors P₂₀₁ and P₂₀₂, the absolute value of thethreshold voltage is increased due to the substrate effect, and henceboth the transistors P₂₀₁ and P₂₀₂ are difficult to be turned on, orthere is a possibility that the on-current becomes small. However, thewhole substrate potentials are divided into the two potentials, i.e.,the potential at SUB₁ and the potential at SUB₂, whereby the increasingof the threshold voltage due to the substrate bias effect is reduced. Ifthe substrate potentials are divided into four blocks and the potentialof each block is controlled, the integration becomes poor but theincreasing of the threshold voltage due to the substrate bias effect canbe further reduced.

[0241] In the semiconductor booster circuit according to the seventhembodiment, since the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage can be madesubstantially zero, the larger boosting capability is obtained ascompared with the sixth embodiment. In particular, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the difference inboosting capability between the sixth embodiment and the seventhembodiment becomes remarkably large. For example, in the case where thepower supply voltage Vdd is about 0.8V to 2.0V, the number n of stagesof the booster circuit required for obtaining a desired output voltageneeds to be greatly increased in the booster circuit of the sixthembodiment due to the voltage drop when transferring the electriccharges from the preceding stage to the subsequent stage, but in thebooster circuit of the seventh embodiment, it is not required at all.For example, in the case where the power supply voltage Vdd is 2.0V, inthe sixth embodiment, the number of stages of the booster circuitrequired for obtaining the output voltage V_(POUT) of 23V is 20 whereasin the booster circuit of the seventh embodiment, the required number ofstages is only 12.

[0242] On the other hand, the booster circuit of the sixth embodiment isadvantageous as compared with the booster circuit of the seventhembodiment in that the configuration is simpler and also only two kindsof clock signals are enough.

[0243] Incidentally, it is to be understood that in the above-mentionedembodiments, the various changes may be made. For example, the number ofstages of the booster circuit is not limited to four in theabove-mentioned embodiment, and hence it may be set to any valuedetermined in accordance with the voltage to be boosted, the circuitscale and the like. In addition, the N-channel depletion type MOStransistors M₁₀₁ to M₁₀₈ are exemplarily employed as the transistorsconstituting the booster circuit in the sixth embodiment and also theP-channel MOS transistors P₂₀₁ to P₂₀₄ are exemplarily employed as thetransistors constituting the booster circuit in the seventh embodiment.However, as for those transistors, other transistors such as N-channelenhancement type MOS transistors may also be employed. For example, theN-channel MOS transistors M₁₀₁ to M₁₀₈ in the sixth embodiment may besubstituted by P-channel MOS transistors which are formed in the N typewell region, and also the power supply terminal N₁₂₀ may be grounded toprovide the negative high voltage generating circuit. In addition, theP-channel MOS transistors P₂₀₁ to P₂₀₄ in the seventh embodiment may besubstituted by N-channel MOS transistors which are formed in the P typewell region to provide the negative high voltage generating circuit.

[0244] In the sixth and seventh embodiments, the substrate terminals ofthe MOS transistors constituting the booster circuit are divided intothe necessary groups, and also are controlled to the differentpotentials for the groups, whereby it is possible to prevent thesubstrate bias effect from occurring. Therefore, the high boostingcapability can be obtained and also the increasing of the circuit areacan be suppressed to the minimum.

1. A semiconductor booster circuit comprising: a plurality of stages,each having a first MOS transistor and a first capacitor having oneterminal connected to a drain terminal of said first MOS transistor,said stages being connected in series by connecting said first MOStransistors of said stages in cascade; and at least one of a firstarrangement wherein a source terminal of said first MOS transistor ofeach of said stages is electrically connected to its substrate, and whensaid plurality of stages are divided into at least two groups, saidsubstrates of said first MOS transistors included in each group areelectrically insulated from said substrates of said first MOStransistors included in another group, and a second arrangement whereinone terminal of a second capacitor is connected to a gate terminal ofsaid first MOS transistor of each of said stages, and first clock signalgenerating means for inputting a first clock signal to the otherterminal of said first capacitor, and second clock signal generatingmeans for inputting a second clock signal having a larger amplitude thana power supply voltage (Vdd) to the other terminal of said secondcapacitor are provided.
 2. A semiconductor booster circuit comprising: aplurality of stages, each having a first MOS transistor and a firstcapacitor having one terminal connected to a drain terminal of saidfirst MOS transistor, said stages being connected in series byconnecting the first MOS transistors of said stages in cascade, whereina source terminal of said first MOS transistor of each of said stages iselectrically connected to its substrate, and when said plurality ofstages are divided into at least two groups, the substrates of saidfirst MOS transistors included in each group are electrically insulatedfrom the substrates of said first MOS transistors included in anotherdifferent group.
 3. A semiconductor booster circuit according to claim2, wherein said first MOS transistors of said plurality of stages areP-channel MOS transistors which are respectively formed in a pluralityof N type well regions which are formed in a surface of a semiconductorsubstrate, and said plurality of N type well regions are electricallyinsulated from one another.
 4. A semiconductor booster circuit accordingto claim 2, wherein each of said stages includes a second capacitorwhich is connected to a gate terminal of said first MOS transistor, anda second MOS transistor which is connected between said gate terminaland said source terminal of said first MOS transistor and has a gateterminal connected to said one terminal of said first capacitor.
 5. Asemiconductor booster circuit according to claim 4, wherein a pair ofclock signals which are in opposite phase with each other arerespectively inputted to the other terminals of said first capacitors inconsecutive two of said stages, and a pair of clock signals arerespectively inputted to the other terminals of said second capacitorsin consecutive two of said stages.
 6. A semiconductor booster circuitaccording to claim 2, wherein a gate terminal of said first MOStransistor of each of said stages is connected to said one terminal ofsaid first capacitor in the subsequent stage, and a pair of clocksignals which are in opposite phase with each other are respectivelyinputted to the other terminals of said first capacitors in theconsecutive two stages.
 7. A semiconductor booster circuit comprising: aplurality of stages, each having a first MOS transistor and a firstcapacitor having one terminal connected to one terminal of said firstMOS transistor, said stages being connected in series by connecting thefirst MOS transistors of said stages in cascade, wherein a sourceterminal of said first MOS transistor of each of said stages iselectrically connected to both its gate terminal and its substrate, andwhen said plurality of stages are divided into at least two groups, saidsubstrates of said first MOS transistors included in each group areelectrically insulated from the substrates of said first MOS transistorsincluded in another different group.
 8. A semiconductor booster circuitaccording to claim 7, wherein said first MOS transistors of saidplurality of stages are P-channel MOS transistors which are respectivelyformed in a plurality of N type well regions which are formed in asurface of a semiconductor substrate, and also said plurality of N typewell regions are electrically insulated from one another.
 9. Asemiconductor booster circuit comprising: a plurality of stages, eachhaving a first MOS transistor, a first capacitor having one terminalconnected to a drain terminal of said first MOS transistor and a secondcapacitor having one terminal connected to a gate terminal of said firstMOS transistor, said stages being connected in series by connecting thefirst MOS transistors of said stages in cascade; first clock signalgenerating means for inputting a first clock signal to the otherterminal of said first capacitor of each stage; and second clock signalforming means for inputting a second clock signal having a largeramplitude than a power supply voltage (Vdd) to the other terminal ofsaid second capacitor.
 10. A semiconductor booster circuit according toclaim 9, wherein the first clock signals which are respectively inputtedto the other terminals of said first capacitors in consecutive two ofsaid stages are in opposite phase with each other.
 11. A semiconductorbooster circuit according to claim 9, wherein each of said stagesfurther includes a second MOS transistor which is connected between saidgate terminal and a source terminal of said first MOS transistor and hasa gate terminal which is connected to the other terminal of saidcapacitor in the subsequent stage.
 12. A semiconductor booster circuitcomprising: a plurality of stages which, each having a first MOStransistor, a first capacitor having one terminal connected to a drainterminal of said first MOS transistor and a second capacitor having oneterminal connected to a gate terminal of said first MOS transistor, saidstages being connected in series by connecting the first MOS transistorsof said stages in cascade wherein a source terminal of said first MOStransistor of each of said stages is electrically connected to itssubstrate, and when said plurality of stages are divided into at leasttwo groups, said substrates of said first MOS transistors included ineach group are electrically insulated from said substrates of said firstMOS transistors included in another different group; first clock signalgenerating means for inputting first clock signal to the other terminalof said first capacitor in each stage; and second clock signalgenerating means for inputting a second clock signal having a largeramplitude than a power supply voltage (Vdd) to the other terminal ofsaid second capacitor in each stage.
 13. A semiconductor booster circuitaccording to claim 12, wherein said first MOS transistors of saidplurality of stages are P-channel MOS transistors which are respectivelyformed in a plurality of N type well regions which are formed in asurface of a semiconductor substrate, and also said plurality of N typewell regions are electrically insulated from one another.
 14. Asemiconductor booster circuit according to claim 12, wherein each ofsaid stages further includes a second MOS transistor which is connectedbetween said gate terminal and said source terminal of said first MOStransistor, and has a gate terminal which is connected to said oneterminal of said first capacitor.
 15. A semiconductor booster circuitaccording to claim 12, wherein said first clock signals which arerespectively inputted to the other terminals of said first capacitors inconsecutive two of said stages are in opposite phase with each other.16. A semiconductor booster circuit comprising: a plurality of stages,each having two first MOS transistors connected in series with eachother and two capacitors each having one terminal connected to a drainor source terminal of one of said first MOS transistor, the seriescircuits of said first MOS transistors of the respective stages beingconnected in series between an input side and an output side, whereinsaid plurality of stages are divided into at least two groups,substrates of said first MOS transistors included in each of the groupsare integrally formed in a conductive substrate portion, and electricalpotentials respectively applied to said substrate portions of saidgroups are controlled independently of one another.
 17. A semiconductorbooster circuit according to claim 16, wherein when said booster circuitis a circuit for generating a positive high voltage, the potential whichis applied to said substrate portion of one group closer to the outputside, is higher than the potential which is applied to said substrateportion of another group.
 18. A semiconductor booster circuit accordingto claim 17, wherein said first MOS transistors which are included inthe stages of each group are P-channel MOS transistors which are formedin an N type well region which is formed in a surface of a semiconductorsubstrate, and said well regions in which said first MOS transistors ofthe stages in the different groups are respectively formed areelectrically insulated from one another.
 19. A semiconductor boostercircuit according to claim 16, wherein when said booster circuit is acircuit for generating a negative high voltage, the absolute value ofthe negative potential which is applied to said substrate portion of onegroup, closer to the input side is higher than that of the negativepotential which is applied to said substrate portion of another group.20. A semiconductor booster circuit according to claim 19, wherein saidfirst MOS transistors which are included in the stages of each group areP-channel MOS transistors which are formed in an N type well regionwhich is formed in a surface of a semiconductor substrate, and said wellregions in which said first MOS transistors of the stages in thedifferent groups are respectively formed are electrically insulated fromone another.
 21. A semiconductor booster circuit according to claim 16,wherein said substrate portion of each of said groups is connected tosaid drain or source terminal of one of said first MOS transistorsincluded in the group nearest to the input side.
 22. A semiconductorbooster circuit according to claim 16, wherein each of said plurality ofstages further includes two second capacitors which have one terminalsconnected to respective gate terminals of said first MOS transistors,and a second MOS transistor which is connected between said gateterminal and said drain or source terminal of each of said first MOStransistors and has a gate terminal which is connected to said oneterminal of said capacitor associated with the first MOS transistor. 23.A semiconductor booster circuit according to claim 22, wherein asubstrate of said second MOS transistor of each of said stages iselectrically connected to said one substrate portion of said group towhich the stage belongs.
 24. A semiconductor booster circuit accordingto claim 22, further comprising means for inputting a pair of firstclock signals which are in opposite phase with each other to the otherterminals of said two first capacitors of each of said stages,respectively, and also inputting a pair of second clock signals to theother terminals of said two second capacitors at different timings,respectively.